ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control4.2.14 c15 registersTable 4-14 shows the 32-bit wide CP15 system control registers when CRn is c15.Table 4-14 c15 register summaryOp1 CRm Op2 Name Reset Description0 c0 0 IL1Data0 UNK Instruction L1 Data n Register on page 4-891 IL1Data1 UNK Instruction L1 Data n Register on page 4-892 IL1Data2 UNK Instruction L1 Data n Register on page 4-89c1 0 DL1Data0 UNK Data L1 Data n Register on page 4-901 DL1Data1 UNK Data L1 Data n Register on page 4-902 DL1Data2 UNK Data L1 Data n Register on page 4-903 DL1Data3 UNK Data L1 Data n Register on page 4-90c4 0 RAMINDEX UNK RAM Index Register on page 4-911 c0 0 L2ACTLR 0x00000000 L2 Auxiliary Control Register on page 4-1003 L2PFR 0x000009B0 L2 Prefetch Control Register on page 4-1034 ACTLR2 0x00000000 Auxiliary Control Register 2 on page 4-1054 c0 0 CBAR - a Configuration Base Address Register on page 4-106a. The reset value depends on the primary input, PERIPHBASE[39:15].4.2.15 64-bit registersTable 4-15 gives a summary of the 64-bit wide CP15 system control registers, accessed by theMCCR and MRRC instructions.CRn Op1 CRm Op2 Name Reset DescriptionTable 4-15 64-bit register summary- 0 c2 - TTBR0 UNK Translation Table Base Register 0, see the ARM ®Architecture Reference Manual ARMv7-A andARMv7-R edition- 1 c2 - TTBR1 UNK Translation Table Base Register 1, see the ARM ®Architecture Reference Manual ARMv7-A andARMv7-R edition- 4 c2 - HTTBR UNK Hyp Translation Table Base Register, see the ARM ®Architecture Reference Manual ARMv7-A andARMv7-R edition- 6 c2 - VTTBR UNK a Virtualization Translation Table Base Register, seethe ARM ® Architecture Reference Manual ARMv7-Aand ARMv7-R edition- 0 c7 - PAR UNK Physical Address Register on page 4-85- 0 c14 - CNTPCT UNK Physical Count Register, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-13ID062913Non-Confidential