ARM Cortex-A15 MPCore Processor Technical Reference Manual

Signal DescriptionsA.10 External debug interfaceThe following sections describe the external debug interface signals:• APB interface signals.• Authentication interface signals on page A-21.• Miscellaneous debug signals on page A-21.A.10.1APB interface signalsTable A-25 shows the APB interface signals.Table A-25 APB interface signalsSignal Type DescriptionnPRESETDBG Input Active-LOW APB reset input:0 Reset APB.1 Do not reset APB.PCLKDBG Input APB clock.PCLKENDBG Input APB clock enable.PADDRDBG[16:2] Input APB address bus bits[16:2].PADDRDBG31 Input APB address bus bit[31]:0 Not an external debugger access.1 External debugger access.PENABLEDBG Input Indicates the second and subsequent cycles of an APB transfer.PRDATADBG[31:0] Output APB read data bus.PREADYDBG Output APB slave ready. An APB slave can assert PREADYDBG to extend a transfer by inserting waitstates.PSELDBG Input Debug registers select:0 Debug registers not selected.1 Debug registers selected.PSLVERRDBG Output APB slave transfer error:0 No transfer error.1 Transfer error.PWDATADBG[31:0] Input APB write data bus.PWRITEDBG Input APB read or write signal:0 Reads from APB.1 Writes to APB.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. A-20ID062913Non-Confidential