ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 2 Memory System7.7.6 Snoop filter supportIn general, the Cortex-A15 MPCore processor can issue either a write-back or an evicttransaction for any cache line that is removed from the L2 cache. You can use these messagesto manage an external snoop filter. However, the snoop filter logic must not depend on an evictmessage for every clean line dropped from the Cortex-A15 MPCore processor caches. In somecircumstances, the Cortex-A15 MPCore processor might not signal an eviction. For example,clean evictions are not guaranteed to occur in all cases for write-through memory types.7.7.7 ACE configurationsThe Cortex-A15 MPCore processor supports the following ACE configurations:• AXI3 mode.• ACE non-coherent, no L3 cache.• ACE non-coherent, with L3 cache.• ACE outer coherent.• ACE inner coherent on page 7-16.AXI3 modeThe AXI3 mode configuration has the following key features:• AXI3-compliant.• ReadNoSnoop is the only AR channel command issued.• WriteNoSnoop is the only AW channel command issued.• No cache maintenance, DVM operations, or barriers issued on the AR channel• No request sent to the processor on the snoop AC channel.ACE non-coherent, no L3 cacheThe ACE non-coherent, no L3 cache configuration has the following key features:• ACE-compliant with no coherent masters on the ACE.• No L3 cache external to the processor.• ReadNoSnoop and barriers are the only AR channel commands issued.• WriteNoSnoop and barriers are the only AW channel commands issued.• No cache maintenance or DVM operations issued on the AR channe.l• No request sent to the processor on the snoop AC channel.ACE non-coherent, with L3 cacheThe ACE non-coherent, with L3 cache configuration has the following key features:• ACE-compliant with no coherent masters on the ACE.• L3 cache external to the processor.• ReadNoSnoop, barriers, and cache maintenance are the only AR channel commandsissued.• WriteNoSnoop and barriers are the only AW channel commands issued.• No DVM operations issued on the AR channel.• No request sent to the processor on the snoop AC channel.ACE outer coherentThe ACE outer coherent configuration has the following key features:• ACE-compliant with coherent masters on the ACE.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 7-15ID062913Non-Confidential