ARM Cortex-A15 MPCore Processor Technical Reference Manual

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Performance Monitor UnitTable 11-2 PMCFGR bit assignments (continued)Bits Name Function[14] CC Cycle counter implemented. This bit is RO:1 Cycle counter is implemented. PMCR.C is writable.[13:8] Size Counter size. This field is RO and reads as b011111:b01111132-bit counters.[7:0] N Number of event counters. This field is RO with a value that indicates the number of implementedevent counters:b00000110 Six counters.NoteThe cycle counter is not included in the value indicated by the N field.The value of HDCR.HPMN has no effect on the value returned by this field.11.4.2 Performance Monitor Control RegisterThe PMCR characteristics are:PurposeProvides information on the Performance Monitors implementation,including the number of counters implemented, and configures andcontrols the counters.Usage constraints The PMCR is:• A read/write register.• Common to the Secure and Non-secure states.• Accessible in Hyp mode, and all modes executing at PL1 whenHDCR.TPM and HDCR.TPMCR are set to 0.• Accessible in User mode only when PMUSERENR.EN is set to 1,HDCR.TPM and HDCR.TPMCR are set to 0.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 11-1 on page 11-4.Figure 11-3 shows the PMCR bit assignments.31 24 23 16 15 11 10 6 5 4 3 2 1 0IMP IDCODE N Reserved DP X D C PEFigure 11-3 PMCR bit assignmentsARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 11-8ID062913Non-Confidential
Performance Monitor UnitTable 11-3 shows the PMCR bit assignments.Table 11-3 PMCR bit assignmentsBits Name Function[31:24] IMP Implementer code:0x41 ARM.This is a read-only field.[23:16] IDCODE Identification code:0x0F Cortex-A15.This is a read-only field.[15:11] N Number of event counters. In Non-secure modes other than Hyp mode, this field reads the valueof HDCR.HPMN. See Hyp Debug Configuration Register on page 4-69. In Secure state and Hypmode, this field returns 0x6 that indicates the number of counters implemented.This is a read-only field.[10:6] - Reserved, UNK/SBZP.[5] DP Disable PMCCNTR when event counting is prohibited:0 Cycle counter operates regardless of the non-invasive debug authenticationsettings. This is the reset value.1 Cycle counter is disabled if the non-invasive debug is not permitted and enabled.This bit is read/write. For more information on prohibited regions, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition.[4] X Export enable. This bit permits events to be exported to another debug device, such as a tracemacrocell, over an event bus:0 Export of events is disabled. This is the reset value.1 Export of events is enabled.This bit is read/write and does not affect the generation of Performance Monitors interrupts, thatcan be implemented as a signal exported from the processor to an interrupt controller.[3] D Clock divider:0 When enabled, PMCCNTR counts every clock cycle. This is the reset value.1 When enabled, PMCCNTR counts every 64 clock cycles.This bit is read/write.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 11-9ID062913Non-Confidential
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®ARM®Cortex -A15 MPCoreProcessorR
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ContentsARM Cortex-A15 MPCore Proce
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Contents11.4 PMU register descripti
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PrefaceAbout this bookThis book is
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Preface(continued)Stylemonospace bo
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PrefaceFeedbackARM welcomes feedbac
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Introduction1.1 About the Cortex-A1
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Introduction1.2.3 Debug architectur
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Introduction1.4 InterfacesThe proce
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Introduction• The L2 tag RAM regi
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IntroductionThe ARM product deliver
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Introduction1.7.5 r1p0 - r2p0The fo
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Introduction• Added L1 data TLB s
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Functional Description2.1 About the
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Functional DescriptionLoad/Store un
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Functional Description2.2 Interface
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Functional Description2.3 Clocking
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Functional DescriptionFigure 2-5 sh
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Functional DescriptionAll resets ar
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Functional DescriptionPowerup reset
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Functional Description• nPRESETDB
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Functional Description• L2 unifie
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Functional DescriptionOn entry into
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Functional DescriptionWhen the proc
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Functional DescriptionNoteFigure 2-
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Functional DescriptionRegional cloc
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Functional DescriptionTable 2-3 Val
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Functional Description4. Release th
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Functional DescriptionDebug power d
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Functional DescriptionNoteAfter a p
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Functional DescriptionThe external
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Programmers Model3.1 About the prog
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Programmers Model3.3 Advanced SIMD
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Programmers ModelYou can use the CP
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Programmers Model3.6 Large Physical
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Programmers Model3.8 Modes of opera
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Chapter 4System ControlThis chapter
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System Control4.2 Register summaryT
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System ControlOp1 CRm Op2 Name Rese
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System ControlTable 4-6 c5 register
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System ControlTable 4-8 c7 register
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System ControlTable 4-10 c9 registe
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System Control4.2.14 c15 registersT
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System ControlName CRn Op1 CRm Op2
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System Control4.2.19 Other system c
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System Control4.2.24 Performance mo
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System Control4.2.26 Virtualization
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System Control4.3 Register descript
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System ControlTo access the CTR, re
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System ControlTable 4-34 shows the
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System Control4.3.12 Memory Model F
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System ControlTable 4-40 ID_MMFR3 b
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System Control31 28 27 24 23 20 19
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System ControlTable 4-43 ID_ISAR2 b
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System ControlConfigurationsAvailab
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System ControlMCR p15, 4, , c0, c0,
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System ControlTable 4-52 SCTLR bit
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System Control31 30 29 28 27 26 25
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System ControlTable 4-53 ACTLR bit
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System ControlTable 4-53 ACTLR bit
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System ControlUsage constraints The
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System Control• The L2 internal a
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System Control31 30 29 28 27 26 25
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System ControlUsage constraints The
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System ControlTable 4-59 HCPTR bit
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System ControlTable 4-61 DFSR bit a
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System ControlTable 4-63 IFSR bit a
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System ControlConfigurationsAvailab
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System Control• UNKNOWN when exec
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System Control31 30 26 25 24 23 22
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System Control• Only accessible f
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System Control31 0DataFigure 4-40 I
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System ControlThe data returned fro
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System ControlThe data returned fro
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System Control31 24 23 21 20 19 18
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System Control4.3.60 L2 Auxiliary C
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System ControlTable 4-74 L2ACTLR bi
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System Control• Is only accessibl
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System ControlTable 4-79 L2MERRSR b
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Memory Management Unit5.1 About the
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Memory Management Unit5.3 TLB match
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Memory Management Unit• The TLB t
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Memory Management Unit5.6 Intermedi
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Memory Management Unit5.7 External
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Level 1 Memory System6.1 About the
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Level 1 Memory System6.3 L1 instruc
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Level 1 Memory System6.4 L1 data me
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Level 1 Memory SystemL1 or L2 cache
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Level 1 Memory SystemExternal globa
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Level 1 Memory System6.5 Program fl
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Level 1 Memory SystemReset:• Disa
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Chapter 7Level 2 Memory SystemThis
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Level 2 Memory System7.2 Cache orga
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Level 2 Memory System7.2.5 Register
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Level 2 Memory SystemNote• The L2
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Level 2 Memory System7.4 L2 cache p
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Level 2 Memory System7.6 Asynchrono
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Level 2 Memory SystemFor certain tr
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Level 2 Memory System7.7.6 Snoop fi
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Level 2 Memory SystemTable 7-6 show
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Chapter 8Generic Interrupt Controll
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Generic Interrupt Controller8.2 GIC
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Generic Interrupt Controller8.2.4 I
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Generic Interrupt Controller8.3 GIC
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Generic Interrupt ControllerOffset
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Generic Interrupt ControllerTable 8
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Generic Interrupt ControllerPrivate
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Generic Interrupt Controller0x1D043
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Generic Interrupt ControllerThe Cor
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Generic Interrupt ControllerTable 8
Page 248 and 249: Generic Interrupt Controller8.3.8 V
Page 250 and 251: Generic Timer9.1 About the Generic
Page 252 and 253: Generic Timer9.3 Generic Timer prog
Page 254 and 255: Chapter 10DebugThis chapter describ
Page 256 and 257: Debug• Operating systems.• Hard
Page 258 and 259: DebugnPRESETDBGThis signal initiali
Page 260 and 261: DebugTable 10-1 CP14 debug register
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Page 264 and 265: DebugTable 10-2 DBGDIDR bit assignm
Page 266 and 267: DebugTable 10-4 shows the DBGDRCR b
Page 268 and 269: DebugConfigurationsAttributesThe pr
Page 270 and 271: DebugTable 10-8 DBGBCR bit assignme
Page 272 and 273: DebugTable 10-10 shows the DBGWCR b
Page 274 and 275: Debug31 12 11 2 1 0ROMADDR[31:12]Re
Page 276 and 277: Debug10.4.12 OS Lock Status Registe
Page 278 and 279: DebugTable 10-15 shows the DBGPRCR
Page 280 and 281: DebugTable 10-16 DBGDSAR bit assign
Page 282 and 283: Debug31 1 0ReservedIntegration mode
Page 284 and 285: DebugTable 10-22 shows the DBGDEVID
Page 286 and 287: Debug10.4.23 Component Identificati
Page 288 and 289: Debug10.6 External debug interfaceT
Page 290 and 291: DebugIf software running on the pro
Page 292 and 293: Performance Monitor Unit11.1 About
Page 294 and 295: Performance Monitor Unit11.3 PMU re
Page 296 and 297: Performance Monitor UnitTable 11-1
Page 304 and 305: Performance Monitor Unit11.5 Effect
Page 308 and 309: Performance Monitor Unit11.7 Interr
Page 310 and 311: Chapter 12Program Trace MacrocellTh
Page 312 and 313: Program Trace Macrocell12.2 PTM opt
Page 314 and 315: Program Trace MacrocellYou can also
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Page 318 and 319: Program Trace Macrocellarchitecture
Page 320 and 321: Program Trace Macrocell12.6 Registe
Page 322 and 323: Program Trace MacrocellTable 12-4 P
Page 324 and 325: Program Trace MacrocellTable 12-5 E
Page 326 and 327: Program Trace MacrocellTable 12-6 E
Page 328 and 329: Program Trace Macrocell31 26 25 24
Page 330 and 331: Program Trace Macrocell12.7.8 Confi
Page 332 and 333: Program Trace Macrocell12.7.10 Auxi
Page 334 and 335: Program Trace Macrocell31 4 3 2 0Re
Page 336 and 337: Program Trace MacrocellTable 12-17
Page 338 and 339: Program Trace Macrocell31 7 60Reser
Page 340 and 341: Program Trace MacrocellThe Componen
Page 342 and 343: Cross Trigger13.1 About the cross t
Page 344 and 345: Cross Trigger13.3 Cortex-A15 CTIIn
Page 346 and 347: Chapter 14NEON and VFP UnitThis cha
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NEON and VFP UnitARM DDI 0438I Copy
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NEON and VFP UnitSee the ARM ® Arc
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NEON and VFP UnitConfigurationsAvai
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NEON and VFP UnitTable 14-5 FPSCR b
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NEON and VFP UnitTable 14-6 MVFR1 b
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NEON and VFP Unit31 30 29 0Reserved
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Signal DescriptionsA.1 About the si
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Signal DescriptionsA.3 Reset signal
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Signal DescriptionsA.5 Generic Inte
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Signal DescriptionsA.6 Generic Time
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Signal DescriptionsA.8 Power manage
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Signal DescriptionsA.9 AXI interfac
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Signal DescriptionsWrite address ch
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Signal DescriptionsTable A-14 Read
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Signal DescriptionsTable A-20 Write
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Signal DescriptionsA.10 External de
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Signal DescriptionsTable A-27 Misce
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Signal DescriptionsA.12 Cross trigg
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Signal DescriptionsA.14 DFT and MBI
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Appendix BRevisionsThis appendix de
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RevisionsTable B-3 Differences betw
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ARM Cortex-A15 MPCore Processor Technical Reference Manual

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