ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-8 c7 register summary (continued)Op1 CRm Op2 Name Reset Description2 DCCISW UNK Clean and invalidate data cache line by set/way, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition4 c8 0 ATS1HR UNK Stage 1 Hyp mode read, see the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition1 ATS1HW UNK Stage 1 Hyp mode write, see the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R editiona. PoU = Point of Unification. If BROADCASTINNER is LOW, the PoU is in the L1 data cache. If BROADCASTINNER is HIGH thenthe PoU is outside of the processor and is dependent on the external memory system.b. PoC = Point of Coherence. The PoC is always outside of the processor and is dependent on the external memory system.4.2.8 c8 registersTable 4-9 shows the 32-bit wide CP15 system control registers when CRn is c8.Table 4-9 c8 register summaryOp1 CRm Op2 Name Reset Description0 c3 0 TLBIALLIS UNK Invalidate entire TLB Inner Shareable, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition1 TLBIMVAIS UNK Invalidate unified TLB entry by MVA and ASID Inner Shareable, see theARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition2 TLBIASIDIS UNK Invalidate unified TLB by ASID match Inner Shareable, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition3 TLBIMVAAIS UNK Invalidate unified TLB entry by MVA all ASID Inner Shareable, see theARM ® Architecture Reference Manual ARMv7-A and ARMv7-R editionc5 0 ITLBIALL UNK Invalidate instruction TLB, see the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition1 ITLBIMVA UNK Invalidate instruction TLB entry by MVA and ASID, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition2 ITLBIASID UNK Invalidate instruction TLB by ASID match, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionc6 0 DTLBIALL UNK Invalidate data TLB, see the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition1 DTLBIMVA UNK Invalidate data TLB entry by MVA and ASID, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition2 DTLBIASID UNK Invalidate data TLB by ASID match, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R editionc7 0 TLBIALL UNK Invalidate unified TLB, see the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition1 TLBIMVA UNK Invalidate unified TLB by MVA and ASID, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-9ID062913Non-Confidential