ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlName CRn Op1 CRm Op2 Reset DescriptionTable 4-24 Performance monitor registers (continued)PMINTENSET 1 UNK Performance Monitor Interrupt Enable Set Register, see theARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionPMINTENCLR 2 UNK Performance Monitor Interrupt Enable Clear Register, see theARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionPMOVSSET 3 UNK Performance Monitor Overflow Flag Status Set Register, seethe ARM ® Architecture Reference Manual ARMv7-A andARMv7-R edition4.2.25 Security Extensions registersTable 4-25 shows the 32-bit wide Security Extensions registers.Name CRn Op1 CRm Op2 Reset DescriptionTable 4-25 Security Extensions registersSCR c1 0 c1 0 0x00000000 Secure Configuration Register on page 4-63SDER 1 UNK Secure Debug Enable Register, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionNSACR 2 0x00000000 a Non-Secure Access Control Register on page 4-65VBAR c12 0 c0 0 0x00000000 b Vector Base Address Register, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionMVBAR 1 UNK Monitor Vector Base Address Register, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-ReditionISR c1 0 UNK Interrupt Status Register, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editiona. The reset value depends on the VFP and NEON configuration. If VFP and NEON are implemented, the reset value is0x00000000. If VFP is implemented but NEON is not implemented, the reset value is 0x00008000. If VFP and NEON are notimplemented, the reset value is 0x00000000.b. The reset value is 0x00000000 for the Secure copy of the register. You must program the Non-secure copy of the register withthe required initial value, as part of the processor boot sequence.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-22ID062913Non-Confidential