ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control4.2.24 Performance monitor registersTable 4-24 shows the 32-bit wide performance monitor registers.Name CRn Op1 CRm Op2 Reset DescriptionTable 4-24 Performance monitor registersPMCR c9 0 c12 0 0x410F3000 Performance Monitor Control Register on page 11-8PMNCNTENSET 1 UNK Performance Monitor Count Enable Set Register, see theARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionPMNCNTENCLR 2 UNK Performance Monitor Count Enable Clear Register, see theARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionPMOVSR 3 UNK Performance Monitor Overflow Flag Status Register, see theARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionPMSWINC 4 UNK Performance Monitor Software Increment Register, see theARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionPMSELR 5 UNK Performance Monitor Event Counter Selection Register, seethe ARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionPMCEID0 6 0x3FFF0F3F Performance Monitor Common Event Identification Register0 on page 11-10PMCEID1 7 0x00000000 Performance Monitor Common Event Identification Register1 on page 11-12PMCCNTR c13 0 UNK Performance Monitor Cycle Count Register, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-ReditionPMXEVTYPER 1 UNK Performance Monitor Event Type Select Register, see theARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionPMXEVCNTR 2 UNK Performance Monitor Event Count Register, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-ReditionPMUSERENR c14 0 0x00000000 Performance Monitor User Enable Register, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-ReditionARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-21ID062913Non-Confidential