ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 2 Memory SystemFor certain transactions, the system must be able to identify which processor generated therequest. This applies to requests affecting the global exclusive monitor in addition to Stronglyordered or Device memory type accesses to peripherals.For non-barrier transactions, ARCACHEM[3:0] and AWCACHEM[3:0] identify whether thememory types are Strongly ordered, Device, or Normal Non-cacheable. See the AMBA AXIProtocol Specification. For these memory types, if ARIDM[5] or AWIDM[5] is 1'b1, then therequest is generated from one of the processors. If ARIDM[5] or AWIDM[5] is 1'b0, therequest is originated from the master connected to the ACP slave port. ARIDM[1:0] orAWIDM[1:0] indicates which processor generated the request.For an exclusive read transaction such as when ARLOCK is asserted, ARID[1:0] indicateswhich processor generated the request. Only processors can generate exclusive read requests,and not the ACP or any other source.For an exclusive write transaction such as AWLOCK asserted, AWID[1:0] indicates whichprocessor generated the request. Only processors can generate exclusive write requests, and notthe ACP or any other source.The system does not rely on specific values of ARID or AWID that correspond with specifictransaction sources or transaction types other than the information described in this section.7.7.3 ACE transfersFor Normal Inner-Cacheable memory transfers initiated from one of the processors, thefollowing transfers are supported on the ACE:• WRAP 8x64-bit read transfers (64-bit ACE only).• WRAP 4x128-bit read transfers (128-bit ACE only).• WRAP 8x64-bit write transfers (64-bit ACE only).• WRAP 4x128-bit write transfers (128-bit ACE only).For Non-Cacheable, Cacheable but not allocated, Strongly-ordered, or Device transactionsinitiated from one of the processors, the following transfers are supported on the ACE:• INCR N (N:1-16) 8-bit read transfers.• INCR N (N:1-16) 16-bit read transfers.• INCR N (N:1-16) 32-bit read transfers.• INCR N (N:1-8) 64-bit read transfers.• INCR N (N:1-4) 128-bit read transfers.• INCR N (N:1-16) 8-bit write transfers.• INCR N (N:1-16) 16-bit write transfers.• INCR N (N:1-16) 32-bit write transfers.• INCR N (N:1-8) 64-bit write transfers.• INCR N (N:1-4) 128-bit write transfers.If there are requests on the Cortex-A15 MPCore ACP port, the following transfers can begenerated on the ACE if comparable requests are received on the ACP:• WRAP N (N:1-16) 8-bit read transfers.• WRAP N (N:1-16) 16-bit read transfers.• WRAP N (N:1-16) 32-bit read transfers.• WRAP N (N:1-8) 64-bit read transfers.• WRAP N (N:1-4) 128-bit read transfers.• WRAP N (N:1-16) 8-bit write transfers.• WRAP N (N:1-16) 16-bit write transfers.• WRAP N (N:1-16) 32-bit write transfers.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 7-13ID062913Non-Confidential