ARM Cortex-A15 MPCore Processor Technical Reference Manual

Signal DescriptionsTable A-27 Miscellaneous debug signals (continued)Signal Type DescriptionDBGROMADDR[39:12] Input Specifies bits[39:12] of the ROM Table physical address.If the address cannot be determined, tie this signal off to 0.This signal is only sampled during reset of the processor.DBGROMADDRV Input Valid signal for DBGROMADDR.If the address cannot be determined, tie this signal LOW.This signal is only sampled during reset of the processor.DBGSELFADDR[39:17] Input Specifies bits[39:17] of the two’s complement signed offset from the ROM Table physicaladdress to the physical address where the debug registers are memory-mapped.If the offset cannot be determined, tie this signal off to 0.This signal is only sampled during reset of the processor.DBGSELFADDRV Input Valid signal for DBGSELFADDR. If the offset cannot be determined, tie this signalLOW.This signal is only sampled during reset of the processor.DBGNOPWRDWN[N:0] Output No powerdown request:0 On a powerdown request, the SoC power controller powers down theprocessor.1 On a powerdown request, the SoC power controller does not power downthe processor.DBGPWRDWNACK[N:0] Output Processor powerdown acknowledge:0 No acknowledge for processor powerdown request.1 Acknowledge for processor powerdown request.DBGPWRDWNREQ[N:0] Input Processor powerdown request:0 No request for processor power down.1 Request for processor power down.DBGPWRUPREQ[N:0] Output Processor powerup request:0 No request for processor power up.1 Request for processor power up.DBGRSTREQ[N:0] Output Warm reset request:0 No request for warm reset.1 Request for warm reset.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. A-22ID062913Non-Confidential