ARM Cortex-A15 MPCore Processor Technical Reference Manual

Generic Interrupt Controller8.3.8 Virtual CPU interface register descriptionsThis section only describes registers whose implementation is specific to the Cortex-A15MPCore processor. All other registers are described in the ARM ® Generic Interrupt ControllerArchitecture Specification. Table 8-14 on page 8-20 provides cross references to individualregisters.VM Active Priority RegisterThe GICV_APR0 characteristics are:PurposeFor software compatibility, this register is present in the virtual CPUinterface. However, in virtualized system, it is not used in the preservingand restoring state.Usage constraints. Reading the content of this register and then writing the same values mustnot change any state because there is no requirement to preserve andrestore state during a powerdown.ConfigurationsAvailable if the GIC is implemented.Attributes See the register summary in Table 8-14 on page 8-20.The Cortex-A15 MPCore processorprocessor implements the GICV_APR0 as an alias ofGICH_APR.VM CPU Interface Identification RegisterThe GICV_IIDR characteristics are:PurposeProvides information about the implementer and revision of the virtualCPU interface.Usage constraints There are no usage constraints.ConfigurationsAvailable if the GIC is implemented.Attributes See the register summary in Table 8-14 on page 8-20.The bit assignments for the VM CPU Interface Identification Register are identical to thecorresponding register in the CPU interface, see CPU Interface Identification Register onpage 8-17.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 8-21ID062913Non-Confidential