ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Controla. This fault is not generated by the Cortex-A15 MPCore processor.DFSR format when using the Long-descriptor translation table formatFigure 4-32 shows the DFSR bit assignments when using the Long-descriptor translation tableformat.31 14 13 12 11 10 9 8 6 5 0Reserved 1StatusReservedReservedWnRExTCMFigure 4-32 DFSR bit assignments for Long-descriptor translation table formatTable 4-61 shows the DFSR bit assignments when using the Long-descriptor translation tableformat.Bits Name Function[31:14] - Reserved, UNK/SBZP.Table 4-61 DFSR bit assignments for Long-descriptor translation table format[13] CM Cache maintenance fault. For synchronous faults, this bit indicates whether a cache maintenanceoperation generated the fault:0 Abort not caused by a cache maintenance operation.1 Abort caused by a cache maintenance operation.On an asynchronous fault, this bit is UNKNOWN.[12] ExT External abort type. This field indicates whether an AXI Decode or Slave error caused an abort:0 External abort marked as DECERR.1 External abort marked as SLVERR.For aborts other than external aborts this bit always returns 0.[11] WnR Write not Read bit. This field indicates whether a write or a read access caused the abort:0 Abort caused by a read access.1 Abort caused by a write access.For faults on CP15 cache maintenance operations, including the VA to PA translation operations,this bit always returns a value of 1.[10] - Reserved, UNK/SBZP.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-77ID062913Non-Confidential