ARM Cortex-A15 MPCore Processor Technical Reference Manual

Generic Interrupt ControllerOffset Name Type Reset Description0x000C GICC_IAR RO 0x000003FF Interrupt Acknowledge Register, see ARM Generic Interrupt ControllerArchitecture Specification0x0010 GICC_EOIR WO - End Of Interrupt Register, see ARM Generic Interrupt ControllerArchitecture Specification0x0014 GICC_RPR RO 0x000000FF Running Priority Register, see ARM Generic Interrupt ControllerArchitecture Specification0x0018 GICC_HPPIR RO 0x000003FF Highest Priority Pending Interrupt Register, see ARM Generic InterruptController Architecture Specification0x001C GICC_ABPR RW c 0x00000003 Aliased Binary Point Register, see ARM Generic Interrupt ControllerArchitecture Specification0x0020 GICC_AIAR RO c 0x000003FF Aliased Interrupt Acknowledge Register, see ARM Generic InterruptController Architecture Specification0x0024 GICC_AEOIR WO c - Aliased End of Interrupt Register, see ARM Generic InterruptController Architecture Specification0x0028 GICC_AHPPIR RO c 0x000003FF Aliased Highest Priority Pending Interrupt Register, see ARM GenericInterrupt Controller Architecture Specification0x00D0 GICC_APR0 RW 0x00000000 Active Priority Register0x00E0 GICC_NSAPR0 RW c 0x00000000 Non-secure Active Priority Register on page 8-170x00FC GICC_IIDR RO 0x0002043B CPU Interface Identification Register on page 8-170x1000 GICC_DIR WO - Deactivate Interrupt Register, see ARM Generic Interrupt ControllerArchitecture Specificationa. S = Secure.b. NS = Non-secure.c. This register is only accessible from a Secure access.Table 8-9 CPU interface register summary (continued)8.3.4 CPU interface register descriptionsThis section only describes registers whose implementation is specific to the Cortex-A15MPCore processor. All other registers are described in the ARM Generic Interrupt ControllerArchitecture Specification. Table 8-9 on page 8-15 provides cross references to individualregisters.Active Priority RegisterThe GICC_APR0 characteristics are:PurposeProvides support for preserving and restoring state in power-managementapplications.Usage constraints. This register is banked to provide Secure and Non-secure copies. Thisensures that Non-secure accesses do not interfere with Secure operation.ConfigurationsAvailable if the GIC is implemented.Attributes See the register summary in Table 8-9 on page 8-15.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 8-16ID062913Non-Confidential