ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlName CRn Op1 CRm Op2 Reset DescriptionTable 4-27 Hyp mode TLB maintenance operations (continued)TLBIALLH c7 0 UNK Invalidate entire Hyp unified TLB, see the ARM ®Architecture Reference Manual ARMv7-A andARMv7-R editionTLBIMVAH 1 UNK Invalidate Hyp unified TLB by MVA, see theARM ® Architecture Reference Manual ARMv7-Aand ARMv7-R editionTLBIALLNSNH 4 UNK Invalidate entire Non-secure Non-Hyp unifiedTLB, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R edition4.2.28 Generic Timer registersSee Chapter 9 Generic Timer for information on the Generic Timer registers.4.2.29 Implementation defined registersTable 4-28 shows the IMPLEMENTATION DEFINED registers. These registers provide test featuresand any required configuration options specific to the Cortex-A15 MPCore processor.Name CRn Op1 CRm Op2 Reset Width DescriptionTable 4-28 Implementation defined registersACTLR c1 0 c0 1 0x00000000 32-bit Auxiliary Control Register on page 4-57L2CTLR c9 1 c0 2 0x00000000 a 32-bit L2 Control Register on page 4-85L2ECTLR 3 0x00000000 32-bit L2 Extended Control Register on page 4-87IL1DATA0 c15 0 c0 0 UNK 32-bit Instruction L1 Data n Register on page 4-89IL1DATA1 1 UNK 32-bit Instruction L1 Data n Register on page 4-89IL1DATA2 2 UNK 32-bit Instruction L1 Data n Register on page 4-89DL1DATA0 c1 0 UNK 32-bit Data L1 Data n Register on page 4-90DL1DATA1 1 UNK 32-bit Data L1 Data n Register on page 4-90DL1DATA2 2 UNK 32-bit Data L1 Data n Register on page 4-90DL1DATA3 3 UNK 32-bit Data L1 Data n Register on page 4-90RAMINDEX c4 0 UNK 32-bit RAM Index Register on page 4-91L2ACTLR 1 c0 0 0x00000000 32-bit L2 Auxiliary Control Register on page 4-100L2PFR 3 0x000009B0 32-bit L2 Prefetch Control Register on page 4-103ACTLR2 4 0x00000000 32-bit Auxiliary Control Register 2 on page 4-105CBAR 4 c0 0 - b 32-bit Configuration Base Address Register on page 4-106CPUMERRSR - 0 c15 - - c 64-bit CPU Memory Error Syndrome Register onpage 4-107L2MERRSR - 1 c15 - - c 64-bit L2 Memory Error Syndrome Register on page 4-109ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-25ID062913Non-Confidential