ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlUsage constraints The SCR is:• A read/write register.• A Restricted access register that exists only in the Secure state.• Only accessible in Secure PL1 modes.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-3 on page 4-5.Figure 4-26 shows the SCR bit assignments.31 10 9 8 7 6 5 4 3 2 1 0ReservedSIFHCESCDnETAWFWEAFIQIRQNSTable 4-55 shows the SCR bit assignments.Bits Name Function[31:10] - Reserved, UNK/SBZP.Figure 4-26 SCR bit assignmentsTable 4-55 SCR bit assignments[9] SIF Secure Instruction Fetch. When the processor is in Secure state, this bit disables instruction fetchesfrom Non-secure memory:0 Secure state instruction fetches from Non-secure memory are permitted. This isthe reset value.1 Secure state instruction fetches from Non-secure memory are not permitted.[8] HCE Hyp Call enable. This bit enables the use of HVC instruction from Non-secure PL1 modes:0 The HVC instruction is UNDEFINED in Non-secure PL1 modes, and UNPREDICTABLEin Hyp mode. This is the reset value.1 The HVC instruction is enabled in Non-secure PL1 modes, and performs a Hyp Call.[7] SCD Secure Monitor Call disable. This bit causes the SMC instruction to be UNDEFINED in Non-securestate:0 The SMC instruction executes normally in Non-secure state, and performs a SecureMonitor Call. This is the reset value.1 The SMC instruction is undefined in Non-secure state.A trap of the SMC instruction to Hyp mode takes priority over the value of this bit. See the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition for more information.[6] nET Not Early Termination. This bit disables early termination of data operations.This bit is not implemented, UNK/SBZP.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-64ID062913Non-Confidential