ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control31 24 23 21 20 19 18 17 14 136 50CPURAMID = 0x12Reserved Physical address [13:6] ReservedIDReservedWayFigure 4-55 RAMINDEX bit assignments for L2 snoop tag RAMThe RAMINDEX address bits for accessing L2 snoop tag RAM are:CPUID[1:0] Processor ID of the executing processor that has access to the L2 snoop tag RAM.WayPA[13:8]PA[7:6]Way select.Row select.Bank select.The data returned from accessing L2 snoop tag RAM are:DL1DATA3 32'b0.DL1DATA2 32'b0.DL1DATA1 Tag ECC[6:0].DL1DATA0 Tag data[28:0].Figure 4-56 shows the RAMINDEX bit assignments for accessing L2 data ECC RAM.31 24 23 22 21 18 17 4 3 0RAMID = 0x13 Way Physical address [17:4]ReservedReservedFigure 4-56 RAMINDEX bit assignments for L2 data ECC RAMThe RAMINDEX address bits for accessing L2 data ECC RAM are:Way[3:0]PA[17:8]PA[7:6]PA[5:4]Way select.Row select.Tag bank select.Data bank select.The data returned from accessing L2 data ECC RAM are:DL1DATA3 32'b0.DL1DATA2 32'b0.DL1DATA1 32'b0.DL1DATA0 Data ECC[15:0].Figure 4-57 on page 4-99 shows the RAMINDEX bit assignments for accessing L2 dirty RAM.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-98ID062913Non-Confidential