ARM Cortex-A15 MPCore Processor Technical Reference Manual

DebugTable 10-14 DBGOSLSR bit assignments (continued)Bits Name Function[2] nTT Not 32-bit access. This bit is always RAZ. It indicates that a 32-bit access is required to write thekey to the OS Lock Access Register.[1] OSLK This bit indicates the status of the OS Lock:0 Lock not set.1 Lock set.The OS Lock is set or cleared by writing to the DBGOSLAR, see OS Lock Access Register onpage 10-22. The OS Lock is set to 1 on a core powerup reset.Setting the OS Lock restricts access to debug registers. See the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R edition for more information.[0] OSLM[0] OS Lock Model implemented bit. This field identifies the form of OS Save and Restoremechanism implemented:b10The processor implements the OS Lock Model but does not implementDBGOSSRR.NoteThis field splits across the two non-contiguous bits in the register.10.4.13 Device Powerdown and Reset Control RegisterThe DBGPRCR characteristics are:PurposeControls processor functionality related to reset and powerdown.Usage constraints There are no usage constraints.ConfigurationsRequired in all configurations.Attributes See the register summary in Table 10-1 on page 10-6.Figure 10-15 shows the DBGPRCR bit assignments.31 4 3 2 1 0ReservedCOREPURQHCWRCWRRCORENPDRQFigure 10-15 DBGPRCR bit assignmentsARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 10-24ID062913Non-Confidential