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ARM Cortex-A15 MPCore Processor Technical Reference Manual

ARM Cortex-A15 MPCore Processor Technical Reference Manual

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Functional Description2.2 InterfacesThe processor has the following external interfaces:• ACE master interface.• ACP slave interface.• APB slave interface.• ATB interface.• Cross trigger interface.• DFT interface on page 2-7.• MBIST controller interface on page 2-7.2.2.1 ACE master interfaceThe processor implements an AMBA 4 AXI Coherency Extensions (ACE) master interface. Seethe <strong>ARM</strong> ® AMBA ® AXI and ACE Protocol Specification AXI3 , AXI4 , and AXI4-Lite , ACEand ACE-Lite for more information.ACE is an extension to the AXI protocol and provides the following enhancements:• Support for hardware coherent caches.• Barrier transactions that guarantee transaction ordering.• Distributed virtual memory messaging, enabling management of a virtual memorysystem.2.2.2 ACP slave interfaceThe processor implements an AMBA 3 AXI Accelerator Coherency Port (ACP) slave interface.See the <strong>ARM</strong> ® AMBA ® AXI and ACE Protocol Specification AXI3 , AXI4 , and AXI4-Lite ,ACE and ACE-Lite for more information.ACP is an implementation of an AMBA 3 AXI slave interface. It supports memory coherentaccesses to the processor memory system, but cannot receive coherent requests, barriers ordistributed virtual memory messages.2.2.3 APB slave interfaceThe processor implements an AMBA 3 APB slave interface that enables access to the debugregisters. See the <strong>ARM</strong> CoreSight Architecture Specification for more information.2.2.4 ATB interfaceThe processor implements dedicated AMBA 3 ATB interfaces for each processor that outputstrace information for debugging. The ATB interface is compatible with the CoreSightarchitecture. See the <strong>ARM</strong> ® CoreSight Architecture Specification for more information.2.2.5 Cross trigger interfaceThe processor implements a single cross trigger channel interface. This external interface isconnected to the CoreSight Cross Trigger Interface (CTI) corresponding to each processorthrough a simplified Cross Trigger Matrix (CTM). See Chapter 13 Cross Trigger for moreinformation.<strong>ARM</strong> DDI 0438I Copyright © 2011-2013 <strong>ARM</strong>. All rights reserved. 2-6ID062913Non-Confidential

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