ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTo access the ID_ISAR1, read the CP15 register with:MRC p15, 0, , c0, c2, 1 ; Read Instruction Set Attribute Register 14.3.17 Instruction Set Attribute Register 2The ID_ISAR2 characteristics are:PurposeProvides information about the instruction set that the processor supports.Usage constraints The ID_ISAR2 is:• A read-only register.• Common to the Secure and Non-secure states.• Only accessible from PL1 or higher.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-2 on page 4-4.Figure 4-15 shows the ID_ISAR2 bit assignments.31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0Reversal_instrsPSR_instrsMultU_instrsMultS_instrsMult_instrsMultiAccessInt_instrsMemHint_instrsLoadStore_instrsTable 4-43 shows the ID_ISAR2 bit assignments.Figure 4-15 ID_ISAR2 bit assignmentsTable 4-43 ID_ISAR2 bit assignmentsBits Name Function[31:28] Reversal_instrs Indicates the supported Reversal instructions:0x2Processor supports REV, REV16, REVSH, and RBIT instructions.[27:24] PSR_instrs Indicates the supported A profile instructions to manipulate the PSR:0x1Processor supports MRS and MSR instructions, and the exception return forms ofdata-processing instructions. See the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition for more information.[23:20] MultU_instrs Indicates the supported advanced unsigned Multiply instructions:0x2Processor supports UMULL, UMLAL, and UMAAL instructions.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-43ID062913Non-Confidential