ARM Cortex-A15 MPCore Processor Technical Reference Manual

NEON and VFP UnitMCR p15, 4, r0, c1, c1, 2ISB3. Set the FPEXC.EN bit to enable Advanced SIMD and VFP:MOV r3, #0x40000000VMSR FPEXC, r3At this point the processor can execute Advanced SIMD and VFP instructions.NoteOperation is UNPREDICTABLE if you configure the Coprocessor Access Control Register(CPACR) such that CP10 and CP11 do not have identical access permissions.14.2.3 Register summaryTable 14-3 gives a summary of the Cortex-A15 Advanced SIMD and VFP system registers.Table 14-3 Advanced SIMD and VFP system registersName Type Reset DescriptionFPSID RO 0x410430F0 See Floating-Point System ID RegisterFPSCR RW 0x00000000 See Floating-Point Status and Control Register on page 14-7MVFR1 RO 0x11111111 See Media and VFP Feature Register 1 on page 14-10MVFR0 RO 0x10110222 See Media and VFP Feature Register 0 on page 14-11FPEXC RW 0x00000000 See Floating-Point Exception Register on page 14-12NoteThe Floating-Point Instruction Registers, FPINST and FPINST2 are not implemented, and anyattempt to access them is UNPREDICTABLE.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition for informationon permitted accesses to the Advanced SIMD and VFP system registers.14.2.4 Register descriptionsThis section describes the Cortex-A15 Advanced SIMD and VFP system registers. Table 14-3provides cross references to individual registers.Floating-Point System ID RegisterThe FPSID characteristics are:PurposeProvides top-level information about the floating-point implementation.Usage constraints Only accessible from PL1 or higher.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 14-6ID062913Non-Confidential