ARM Cortex-A15 MPCore Processor Technical Reference Manual

NEON and VFP Unit14.2 Programmers model for NEON and VFP unitThis section describes the programmers model for the Cortex-A15 NEON and VFP unit in:• Accessing the Advanced SIMD and VFP feature identification registers.• Enabling Advanced SIMD and VFP extensions.• Register summary on page 14-6.• Register descriptions on page 14-6.14.2.1 Accessing the Advanced SIMD and VFP feature identification registersSoftware can identify the versions of the ARMv7 Advanced SIMD and VFP extensions, and thefeatures they provide, using the feature identification registers. These registers reside in thecoprocessor space for coprocessors CP10 and CP11.You can access the feature identification registers using the VMRS and VMSR instructions, forexample:VMRS , FPSID ; Read Floating-Point System ID RegisterVMRS , MVFR0 ; Read Media and VFP Feature Register 0VMRS , MVFR1 ; Read Media and VFP Feature Register 1Table 14-2 lists the feature identification registers for the Advanced SIMD and VFP extensions.Table 14-2 Advanced SIMD and VFP feature identification registersNameDescriptionFPSID See Floating-Point System ID Register on page 14-6MVFR0 See Media and VFP Feature Register 0 on page 14-11MVFR1 See Media and VFP Feature Register 1 on page 14-1014.2.2 Enabling Advanced SIMD and VFP extensionsFrom reset, both the Advanced SIMD and VFP extensions are disabled. Any attempt to executeeither an Advanced SIMD or VFP instruction results in an Undefined Instruction exceptionbeing taken. To enable software access to the Advanced SIMD and VFP features, ensure that:• Access to CP10 and CP11 is enabled for the appropriate privilege level. See CoprocessorAccess Control Register on page 4-62.• If Non-secure access to the Advanced SIMD or VFP features is required, the access bitsfor CP10 and CP11 in the NSACR are set to 1. See Non-Secure Access Control Registeron page 4-65.• If Hyp mode access to the Advanced SIMD or VFP features is required, the trap bits forCP10 and CP11 in the HCPTR are set to 0. See Hyp Coprocessor Trap Register onpage 4-71.To enable Advanced SIMD and VFP operations, software must set the FPEXC.EN bit to 1. SeeFloating-Point Exception Register on page 14-12.When Advanced SIMD and VFP operation is disabled because FPEXC.EN is 0, all AdvancedSIMD and VFP instructions are treated as UNDEFINED except for execution of the following inprivileged modes:• A VMSR to the FPEXC or FPSID register.• A VMRS from the FPEXC, FPSID, MVFR0 or MVFR1 register.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 14-4ID062913Non-Confidential