ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0Jazelle_instrsInterwork_instrsImmediate_instrsIfThen_instrsExtend_instrsExcept_AR_instrsExcept_instrsEndian_instrsTable 4-42 shows the ID_ISAR1 bit assignments.Figure 4-14 ID_ISAR1 bit assignmentsTable 4-42 ID_ISAR1 bit assignmentsBits Name Function[31:28] Jazelle_instrs Indicates the supported Jazelle extension instructions:0x1 Processor supports BXJ instruction, and the J bit in the PSR.[27:24] Interwork_instrs Indicates the supported Interworking instructions.0x3 Processor supports:• BX instruction, and the T bit in the PSR.• BLX instruction, and PC loads have BX-like behavior.• Data-processing instructions in the ARM instruction set with the PC as thedestination and the S bit clear have BX-like behavior.[23:20] Immediate_instrs Indicates support for data-processing instructions with long immediates.0x1 Processor supports:• MOVT instruction.• MOV instruction encodings with zero-extended 16-bit immediates.• Thumb ADD and SUB instruction encodings with zero-extended 12-bitimmediates, and other ADD, ADR, and SUB encodings cross-referenced by thepseudocode for those encodings.[19:16] IfThen_instrs Indicates the supported If-Then instructions in the Thumb instruction set:0x1 Processor supports the IT instructions, and the IT bits in the PSRs.[15:12] Extend_instrs Indicates the supported Extend instructions.0x2 Processor supports:• SXTB, SXTH, UXTB, and UXTH instructions.• SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16, UXTAB, UXTAB16, and UXTAH instructions.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-Redition for more information.[11:8] Except_AR_instrs Indicates the supported A and R profile exception-handling instructions:0x1 Processor supports SRS, RFE, and CPS instructions.[7:4] Except_instrs Indicates the supported exception-handling instructions in the ARM instruction set:0x1 Processor supports LDM (exception return), LDM (user registers), and STM (userregisters) instructions.[3:0] Endian_instrs Indicates the supported Endian instructions:0x1 Processor supports SETEND instruction, and the E bit in the PSRs.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-42ID062913Non-Confidential