ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-57 HSCTLR bit assignments (continued)Bits Name Function[2] C Cache enable bit. This is a global enable bit for data and unified caches, for memory accessesmade in Hyp mode:0 Data and unified caches disabled.1 Data and unified caches enabled.[1] A Alignment bit. This is the enable bit for Alignment fault checking, for memory accesses made inHyp mode:0 Alignment fault checking disabled.1 Alignment fault checking enabled.[0] M MMU enable bit. This is a global enable bit for the PL2 stage 1 MMU:0 PL2 stage 1 MMU disabled.1 PL2 stage 1 MMU enabled.To access the HSCTLR, read or write the CP15 register with:MRC p15, 4, , c1, c0, 0; Read Hyp System Control RegisterMCR p15, 4, , c1, c0, 0; Write Hyp System Control Register4.3.33 Hyp Auxiliary Control RegisterThe processor does not implement HACTLR, so this register is UNK/SBZP in Hyp mode andin Monitor mode when SCR.NS is 1.4.3.34 Hyp Debug Configuration RegisterThe HDCR characteristics are:PurposeControls the trapping to Hyp mode of Non-secure accesses, at PL1 orlower, to functions provided by the debug and trace architectures.Usage constraints The HDCR is:• A read/write register.• Only accessible from Hyp mode or from Monitor mode whenSCR.NS is 1.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-3 on page 4-5.Figure 4-29 shows the HDCR bit assignments.31 12 11 10 9 8 7 6 5 4 0ReservedHPMNTPMCRTPMHPMETDETDATDOSATDRAFigure 4-29 HDCR bit assignmentsARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-69ID062913Non-Confidential