ARM Cortex-A15 MPCore Processor Technical Reference Manual

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Performance Monitor UnitTable 11-3 PMCR bit assignments (continued)Bits Name Function[2] C Clock counter reset:0 No action.1 Reset PMCCNTR to 0.NoteResetting PMCCNTR does not clear the PMCCNTR overflow bit to 0. See the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition for more information.This bit is write-only, and always RAZ.[1] P Event counter reset:0 No action.1 Reset all event counters, not including PMCCNTR, to 0.In Non-secure modes other than Hyp mode, a write of 1 to this bit does not reset event countersthat the HDCR.HPMN field reserves for Hyp mode use. See Hyp Debug Configuration Registeron page 4-69.In Secure state and Hyp mode, a write of 1 to this bit resets all the event counters.[0] E Enable bit:0 All counters, including PMCCNTR, are disabled. This is the reset value.1 All counters are enabled.This bit does not disable or enable, counting by event counters reserved for Hyp mode byHDCR.HPMN. It also does not suppress the generation of performance monitor overflowinterrupt requests by those counters.This bit is read/write.To access the PMCR, read or write the CP15 registers with:MRC p15, 0, , c9, c12, 0; Read Performance Monitor Control RegisterMCR p15, 0, , c9, c12, 0; Write Performance Monitor Control Register11.4.3 Performance Monitor Common Event Identification Register 0The PMCEID0 characteristics are:PurposeDefines which common architectural and common micro-architecturalfeature events are implemented.Usage constraints The PMCEID0 is:• A read-only register.• Common to the Secure and Non-secure states.• Accessible in Hyp mode and all modes executing at PL1 whenHDCR.TPM is set to 0.• Accessible in User mode only when PMUSERENR.EN is set to 1and HDCR.TPM is set to 0.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 11-1 on page 11-4.Table 11-4 on page 11-11 shows the PMCEID0 bit assignments with event implemented or notimplemented when the associated bit is set to 1 or 0.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 11-10ID062913Non-Confidential
Performance Monitor UnitPMCEID1[31:0] is reserved.Table 11-4 Common Event Identification Register 0 bit assignmentsBit Event number Event implemented if set to 1 or not implemented if set to 0[31] 0x1F Reserved.[30] 0x1E[29] 0x1D Bus cycle. This event is implemented.[28] 0x1C Instruction architecturally executed, condition check pass, write to translation table base. This event isimplemented.[27] 0x1B Instruction speculatively executed. This event is implemented.[26] 0x1A Local memory error. This event is implemented.[25] 0x19 Bus access. This event is implemented.[24] 0x18 Level 2 data cache write-back. This event is implemented.[23] 0x17 Level 2 data cache refill. This event is implemented.[22] 0x16 Level 2 data cache access. This event is implemented.[21] 0x15 Level 1 data cache write-back. This event is implemented.[20] 0x14 Level 1 instruction cache access. This event is implemented.[19] 0x13 Data memory access. This event is implemented.[18] 0x12 Predictable branch speculatively executed. This bit is RAO.[17] 0x11 Cycle, this bit is RAO.[16] 0x10 Mispredicted or not predicted branch speculatively executed. This bit is RAO.[15] 0x0F Instruction architecturally executed, condition check pass, unaligned load or store. This event is notimplemented.[14] 0x0E Instruction architecturally executed, condition check pass, procedure return. This event is notimplemented.[13] 0x0D Instruction architecturally executed, immediate branch. This event is not implemented.[12] 0x0C Instruction architecturally executed, condition check pass, software change of the PC. This event is notimplemented.[11] 0x0B Instruction architecturally executed, condition check pass, write to CONTEXTIDR. This event isimplemented.[10] 0x0A Instruction architecturally executed, condition check pass, exception return. This event is implemented.[9] 0x09 Exception taken. This event is implemented.[8] 0x08 Instruction architecturally executed, this bit is RAO.[7] 0x07 Instruction architecturally executed, condition check pass, store. This event is not implemented.[6] 0x06 Instruction architecturally executed, condition check pass, load. This event is not implemented.[5] 0x05 Level 1 data TLB refill. This event is implemented.[4] 0x04 Level 1 data cache access. This bit is RAO.[3] 0x03 Level 1 data cache refill. This bit is RAO.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 11-11ID062913Non-Confidential
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®ARM®Cortex -A15 MPCoreProcessorR
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ContentsARM Cortex-A15 MPCore Proce
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Contents11.4 PMU register descripti
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PrefaceAbout this bookThis book is
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Preface(continued)Stylemonospace bo
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PrefaceFeedbackARM welcomes feedbac
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Introduction1.1 About the Cortex-A1
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Introduction1.2.3 Debug architectur
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Introduction1.4 InterfacesThe proce
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Introduction• The L2 tag RAM regi
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IntroductionThe ARM product deliver
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Introduction1.7.5 r1p0 - r2p0The fo
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Introduction• Added L1 data TLB s
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Functional Description2.1 About the
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Functional DescriptionLoad/Store un
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Functional Description2.2 Interface
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Functional Description2.3 Clocking
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Functional DescriptionFigure 2-5 sh
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Functional DescriptionAll resets ar
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Functional DescriptionPowerup reset
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Functional Description• nPRESETDB
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Functional Description• L2 unifie
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Functional DescriptionOn entry into
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Functional DescriptionWhen the proc
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Functional DescriptionNoteFigure 2-
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Functional DescriptionRegional cloc
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Functional DescriptionTable 2-3 Val
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Functional Description4. Release th
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Functional DescriptionDebug power d
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Functional DescriptionNoteAfter a p
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Functional DescriptionThe external
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Programmers Model3.1 About the prog
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Programmers Model3.3 Advanced SIMD
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Programmers ModelYou can use the CP
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Programmers Model3.6 Large Physical
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Programmers Model3.8 Modes of opera
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Chapter 4System ControlThis chapter
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System Control4.2 Register summaryT
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System ControlOp1 CRm Op2 Name Rese
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System ControlTable 4-6 c5 register
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System ControlTable 4-8 c7 register
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System ControlTable 4-10 c9 registe
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System Control4.2.14 c15 registersT
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System ControlName CRn Op1 CRm Op2
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System Control4.2.19 Other system c
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System Control4.2.24 Performance mo
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System Control4.2.26 Virtualization
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System Control4.3 Register descript
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System ControlTo access the CTR, re
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System ControlTable 4-34 shows the
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System Control4.3.12 Memory Model F
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System ControlTable 4-40 ID_MMFR3 b
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System Control31 28 27 24 23 20 19
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System ControlTable 4-43 ID_ISAR2 b
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System ControlConfigurationsAvailab
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System ControlMCR p15, 4, , c0, c0,
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System ControlTable 4-52 SCTLR bit
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System Control31 30 29 28 27 26 25
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System ControlTable 4-53 ACTLR bit
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System ControlTable 4-53 ACTLR bit
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System ControlUsage constraints The
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System Control• The L2 internal a
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System Control31 30 29 28 27 26 25
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System ControlUsage constraints The
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System ControlTable 4-59 HCPTR bit
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System ControlTable 4-61 DFSR bit a
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System ControlTable 4-63 IFSR bit a
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System ControlConfigurationsAvailab
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System Control• UNKNOWN when exec
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System Control31 30 26 25 24 23 22
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System Control• Only accessible f
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System Control31 0DataFigure 4-40 I
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System ControlThe data returned fro
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System ControlThe data returned fro
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System Control31 24 23 21 20 19 18
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System Control4.3.60 L2 Auxiliary C
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System ControlTable 4-74 L2ACTLR bi
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System Control• Is only accessibl
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System ControlTable 4-79 L2MERRSR b
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Memory Management Unit5.1 About the
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Memory Management Unit5.3 TLB match
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Memory Management Unit• The TLB t
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Memory Management Unit5.6 Intermedi
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Memory Management Unit5.7 External
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Level 1 Memory System6.1 About the
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Level 1 Memory System6.3 L1 instruc
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Level 1 Memory System6.4 L1 data me
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Level 1 Memory SystemL1 or L2 cache
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Level 1 Memory SystemExternal globa
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Level 1 Memory System6.5 Program fl
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Level 1 Memory SystemReset:• Disa
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Chapter 7Level 2 Memory SystemThis
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Level 2 Memory System7.2 Cache orga
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Level 2 Memory System7.2.5 Register
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Level 2 Memory SystemNote• The L2
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Level 2 Memory System7.4 L2 cache p
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Level 2 Memory System7.6 Asynchrono
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Level 2 Memory SystemFor certain tr
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Level 2 Memory System7.7.6 Snoop fi
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Level 2 Memory SystemTable 7-6 show
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Chapter 8Generic Interrupt Controll
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Generic Interrupt Controller8.2 GIC
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Generic Interrupt Controller8.2.4 I
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Generic Interrupt Controller8.3 GIC
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Generic Interrupt ControllerOffset
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Generic Interrupt ControllerTable 8
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Generic Interrupt ControllerPrivate
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Generic Interrupt Controller0x1D043
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Generic Interrupt ControllerThe Cor
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Generic Interrupt ControllerTable 8
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Generic Interrupt Controller8.3.8 V
Page 250 and 251: Generic Timer9.1 About the Generic
Page 252 and 253: Generic Timer9.3 Generic Timer prog
Page 254 and 255: Chapter 10DebugThis chapter describ
Page 256 and 257: Debug• Operating systems.• Hard
Page 258 and 259: DebugnPRESETDBGThis signal initiali
Page 260 and 261: DebugTable 10-1 CP14 debug register
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Page 264 and 265: DebugTable 10-2 DBGDIDR bit assignm
Page 266 and 267: DebugTable 10-4 shows the DBGDRCR b
Page 268 and 269: DebugConfigurationsAttributesThe pr
Page 270 and 271: DebugTable 10-8 DBGBCR bit assignme
Page 272 and 273: DebugTable 10-10 shows the DBGWCR b
Page 274 and 275: Debug31 12 11 2 1 0ROMADDR[31:12]Re
Page 276 and 277: Debug10.4.12 OS Lock Status Registe
Page 278 and 279: DebugTable 10-15 shows the DBGPRCR
Page 280 and 281: DebugTable 10-16 DBGDSAR bit assign
Page 282 and 283: Debug31 1 0ReservedIntegration mode
Page 284 and 285: DebugTable 10-22 shows the DBGDEVID
Page 286 and 287: Debug10.4.23 Component Identificati
Page 288 and 289: Debug10.6 External debug interfaceT
Page 290 and 291: DebugIf software running on the pro
Page 292 and 293: Performance Monitor Unit11.1 About
Page 294 and 295: Performance Monitor Unit11.3 PMU re
Page 296 and 297: Performance Monitor UnitTable 11-1
Page 304 and 305: Performance Monitor Unit11.5 Effect
Page 308 and 309: Performance Monitor Unit11.7 Interr
Page 310 and 311: Chapter 12Program Trace MacrocellTh
Page 312 and 313: Program Trace Macrocell12.2 PTM opt
Page 314 and 315: Program Trace MacrocellYou can also
Page 316 and 317: Program Trace Macrocell12.5 PTM pro
Page 318 and 319: Program Trace Macrocellarchitecture
Page 320 and 321: Program Trace Macrocell12.6 Registe
Page 322 and 323: Program Trace MacrocellTable 12-4 P
Page 324 and 325: Program Trace MacrocellTable 12-5 E
Page 326 and 327: Program Trace MacrocellTable 12-6 E
Page 328 and 329: Program Trace Macrocell31 26 25 24
Page 330 and 331: Program Trace Macrocell12.7.8 Confi
Page 332 and 333: Program Trace Macrocell12.7.10 Auxi
Page 334 and 335: Program Trace Macrocell31 4 3 2 0Re
Page 336 and 337: Program Trace MacrocellTable 12-17
Page 338 and 339: Program Trace Macrocell31 7 60Reser
Page 340 and 341: Program Trace MacrocellThe Componen
Page 342 and 343: Cross Trigger13.1 About the cross t
Page 344 and 345: Cross Trigger13.3 Cortex-A15 CTIIn
Page 346 and 347: Chapter 14NEON and VFP UnitThis cha
Page 348 and 349: NEON and VFP UnitARM DDI 0438I Copy
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NEON and VFP UnitSee the ARM ® Arc
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NEON and VFP UnitConfigurationsAvai
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NEON and VFP UnitTable 14-5 FPSCR b
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NEON and VFP UnitTable 14-6 MVFR1 b
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NEON and VFP Unit31 30 29 0Reserved
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Signal DescriptionsA.1 About the si
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Signal DescriptionsA.3 Reset signal
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Signal DescriptionsA.5 Generic Inte
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Signal DescriptionsA.6 Generic Time
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Signal DescriptionsA.8 Power manage
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Signal DescriptionsA.9 AXI interfac
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Signal DescriptionsWrite address ch
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Signal DescriptionsTable A-14 Read
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Signal DescriptionsTable A-20 Write
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Signal DescriptionsA.10 External de
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Signal DescriptionsTable A-27 Misce
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Signal DescriptionsA.12 Cross trigg
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Signal DescriptionsA.14 DFT and MBI
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Appendix BRevisionsThis appendix de
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RevisionsTable B-3 Differences betw
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ARM Cortex-A15 MPCore Processor Technical Reference Manual

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