ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 1 Memory SystemL1 or L2 cache, the line is not allocated into that cache. For a read that misses all caches, therequired data is read to satisfy the memory request, but the line is not added to the cache. For awrite that misses in all caches, the modified bytes are updated in memory.NoteThe No-Allocate allocation hint is only a performance hint. The Cortex-A15 MPCore processormight in some cases, allocate Write-Back No-Allocate lines into the L1 data cache or the L2.Write-ThroughThe Cortex-A15 MPCore processor memory system treats all Write-Through pages asWrite-Through No-Allocate. This means that no cache line from any Write-Through pageallocates in any L1 data or L2 cache. Because it is not legal to map a physical page with multiplecacheability attributes, no Write-Through page can be brought into the cache from a differentvirtual address mapping. Therefore, memory requests for Write-Through cache lines are notlooked-up in the cache. They are sent directly to the AXI master interface.Memory that is inner or outer shared and inner Write-Through are treated as innerNon-Cacheable and outer Non-Cacheable. Memory requests to memory of this type generateReadNoSnoop and WriteNoSnoop system-shareable requests on the ACE interconnect.Non-CacheableNormal Non-Cacheable memory is not looked-up in any cache. The requests are sent directly tomemory. Read requests might over-read in memory, for example, reading 64 bytes of memoryfor a 4-byte access, and might satisfy multiple memory requests with a single external memoryaccess. Write requests might be merged with other write requests to the same bytes or nearbybytes.Memory that is inner or outer shared and inner Non-Cacheable are treated as innerNon-Cacheable and outer Non-Cacheable. Memory requests to memory of this type generateReadNoSnoop and WriteNoSnoop system-shareable requests on the ACE interconnect.Strongly-ordered and DeviceStrongly-ordered and Device memory types are used for communicating with input and outputdevices and memory-mapped peripherals. They are not looked-up in any cache.For the Cortex-A15 MPCore processor, there is no distinction between shareable andnonshareable devices. Both Device and Strongly-ordered memory types are ordered together.All the memory operations for a single instruction can be sent to the interconnect as a burstrequest. No Strongly-ordered or Device read request on the interconnect can cross an aligned64-byte boundary. In addition, no Strongly-ordered or Device write request on the interconnectcan cross an aligned 16-byte boundary.6.4.2 CoherenceAll memory requests for pages that are marked as Inner Shareable in the page tables and areWrite-Back Cacheable, regardless of allocation policy, are coherent in all the caches thatcomprise the inner domain. At a minimum, this includes the L1 data cache of the executing core,the L2 cache, and all other L1 data caches in the Cortex-A15 MPCore processor. The innerdomain might contain additional caches outside the Cortex-A15 MPCore processor dependingon how the system is configured.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 6-8ID062913Non-Confidential