ARM Cortex-A15 MPCore Processor Technical Reference Manual

Signal DescriptionsA.4 Configuration signalsSignal Type DescriptionTable A-3 shows the configuration signals. The value of N is one less than the number ofprocessors in your design.Table A-3 Configuration signalsCFGEND[N:0] Input Individual processor control of the endianness configuration at reset. It sets the initial value of theEE bit in the CP15 System Control Register (SCTLR):0 EE bit is LOW.1 EE bit is HIGH.This signal is only sampled during reset of the processor.CFGTE[N:0] Input Individual processor control of the default exception handling state. It sets the initial value of theTE bit in the CP15 System Control Register (SCTLR):0 TE bit is LOW.1 TE bit is HIGH.This signal is only sampled during reset of the processor.CLUSTERID[3:0] Input Value read in the Cluster ID field, bits[11:8], of the CP15 processor Affinity Register (MPDIR).This signal is only sampled during reset of the processor.IMINLN Input Individual processor control of the instruction cache minimum line size at reset. It sets the initialvalue of the IminLine field in the CP15 Cache Type Register (CTR):0 32-bytes.1 64-bytes.This signal is only sampled during reset of the processor.VINITHI[N:0] Input Individual processor control of the location of the exception vectors at reset. It sets the initialvalue of the V bit in the CP15 System Control Register (SCTLR):0 Exception vectors start at address 0x00000000.1 Exception vectors start at address 0xFFFF0000.This signal is only sampled during reset of the processor.CP15SDISABLE[N:0] Input Disable write access to some secure CP15 registers.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. A-5ID062913Non-Confidential