ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control31 30 26 25 24 23 22 21 20 13 12 11 10 9 8 6 5 4 3 2 0ReservedReservedECC and parity enableReservedInterrupt Controller presentNumber of CPUsL2RSTDISABLE monitorData RAM latencyReservedData RAM setupTag RAM latencyTag RAM setupData RAM sliceTag RAM sliceFigure 4-38 L2CTLR bit assignmentsTable 4-69 shows the L2CTLR bit assignments.Table 4-69 L2CTLR bit assignmentsBits Name Function[31] L2RSTDISABLE monitor Monitors the L2 hardware reset disable pin, L2RSTDISABLE:0 L2 valid RAM contents are reset by hardware.1 L2 valid RAM contents are not reset by hardware.This bit is read-only and the reset value is determined by the primary input,L2RSTDISABLE.[30:26] - Reserved, RAZ/WI.[25:24] Number of processors Number of processors present:b00One processor, CPU0.b01Two processors, CPU0 and CPU1.b10Three processors, CPU0, CPU1, and CPU2.b11Four processors, CPU0, CPU1, CPU2, and CPU3.These bits are read-only and the reset value of this field is set to the number of processorspresent in the configuration.[23] Interrupt Controller Interrupt Controller:0 Interrupt Controller not present.1 Interrupt Controller present.This is a read-only bit and the reset value depends on whether the Interrupt Controller ispresent.[22] - Reserved, RAZ/WI.[21] ECC and parity enable ECC and parity enable bit in L1 and L2 caches:0 Disables ECC and parity. This is the reset value.1 Enables ECC and parity.If ECC/parity is not implemented in L1 and L2 caches, this bit is RAZ/WI.[20:13] - Reserved, RAZ/WI.[12] Tag RAM slice L2 tag RAM slice:0 0 slice.1 1 slice.This is a read-only bit and the reset value of this field is set to the number of tag RAM slicepresent in the configuration. See Register slice support for large cache sizes on page 7-5 formore information.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-86ID062913Non-Confidential