ARM Cortex-A15 MPCore Processor Technical Reference Manual

Signal DescriptionsWrite address channel signalsTable A-10 shows the write address channel signals for the AXI master interface.Table A-10 Write address channel signalsSignal Type DescriptionAWADDRM[39:0] Output AddressAWBARM[1:0] Output Barrier typeAWBURSTM[1:0] Output Burst typeAWCACHEM[3:0] Output Cache typeAWDOMAINM[1:0] Output Domain typeAWIDM[5:0] Output Request IDAWLENM[7:0] Output Burst lengthAWLOCKM Output Lock typeAWPROTM[2:0] Output Protection typeAWREADYM Input Address readyAWSIZEM[2:0] Output Burst sizeAWSNOOPM[2:0] Output Snoop request typeAWUSERM[1:0] Output User signals:b00b01b10b11SharedCleanUniqueCleanSharedDirtyUniqueDirtyAWVALIDM Output Address validWrite data channel signalsTable A-11 shows the write data signals for the AXI master interface.Table A-11 Write data channel signalsSignal Type DescriptionWDATAM[127:0] Output Write dataWIDM[5:0] Output Write IDWLASTM Output Write lastWREADYM Input Write readyWSTRBM[15:0] Output Write strobesWVALIDM Output Write validARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. A-14ID062913Non-Confidential