ARM Cortex-A15 MPCore Processor Technical Reference Manual

Functional DescriptionDebug power domainIf the Cortex-A15 MPCore processor is running in an environment where debug facilities arenot required for any of the processors in the multiprocessor, you can reduce leakage power byturning off the power to the debug unit in the PCLKDBG domain.To enable the debug unit to be powered down, the implementation must place the unit on aseparately controlled power supply. In addition, you must clamp the outputs of the debug unitto benign values while the unit is powered down, to indicate that the unit is idle.To power down the Debug APB PCLKDBG power domain, apply the following sequence:1. Activate the debug output clamps by asserting the nISOLATEPDBG input LOW.2. Remove power from the debug PCLKDBG domain.NoteIf the debug output clamps are released without following the specified debug powerupsequence, the results are UNPREDICTABLE.To power up the Debug APB PCLKDBG power domain, apply the following sequence:1. Assert nPRESETDBG.2. Apply power to the debug PCLKDBG power domain while keeping nPRESETDBGasserted.3. Release the debug output clamps by deasserting nISOLATEPDBG.4. If the SoC uses the debug hardware, deassert nPRESETDBG.External debug over power downThe Cortex-A15 MPCore processor provides support for external debug over power down. Ifany or all of the processors are powered down, the SoC can still use the debug facilities if thedebug PCLKDBG domain is powered up.To enable external debug over power down, the implementation must place the processor andthe debug PCLKDBG unit on separately controlled power supplies. If the processor is powereddown while the debug PCLKDBG unit is powered up, you must clamp all outputs from theprocessor power domain to the debug power domain to benign values, to indicate that theprocessor is idle.To power down the processor and the NEON and VFP power domains for external debug overpowerdown support, apply the following additional step to the processor and NEON and VFPpowerdown sequence, as described in Processor power domain on page 2-30, afterSTANDBYWFI is asserted in step 7:• Assert DBGPWRDWNREQ to indicate that the processor debug resources are notavailable for APB accesses. Wait for DBGPWRDWNACK to be asserted.When power is removed from the processor and NEON and VFP power domains, keep thedebug PCLKDBG unit powered up.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 2-34ID062913Non-Confidential