ARM Cortex-A15 MPCore Processor Technical Reference Manual

Generic Interrupt ControllerOffset Name Type Reset DescriptionTable 8-3 Distributor register summary (continued)0xF10 - 0xF1C GICD_CPENDSGIRn RW 0x00000000 SGI Clear-Pending Registers, see ARM GenericInterrupt Controller Architecture Specification0xF20 - 0xF2C GICD_SPENDSGIRn RW 0x00000000 SGI Set-Pending Registers, see ARM GenericInterrupt Controller Architecture Specification0xFD0 GICD_PIDR4 RO 0x04 Peripheral ID4 Register, see ARM GenericInterrupt Controller Architecture Specification0xFD4 GICD_PIDR5 RO 0x00 Peripheral ID5 Register, see ARM GenericInterrupt Controller Architecture Specification0xFD8 GICD_PIDR6 RO 0x00 Peripheral ID6 Register, see ARM GenericInterrupt Controller Architecture Specification0xFDC GICD_PIDR7 RO 0x00 Peripheral ID7 Register, see ARM GenericInterrupt Controller Architecture Specification0xFE0 GICD_PIDR0 RO 0x90 Peripheral ID0 Register, see ARM GenericInterrupt Controller Architecture Specification0xFE4 GICD_PIDR1 RO 0xB4 Peripheral ID1 Register, see ARM GenericInterrupt Controller Architecture Specification0xFE8 GICD_PIDR2 RO 0x2B Peripheral ID2 Register, see ARM GenericInterrupt Controller Architecture Specification0xFEC GICD_PIDR3 RO 0x00 Peripheral ID3 Register, see ARM GenericInterrupt Controller Architecture Specification0xFF0 GICD_CIDR0 RO 0x0D Component ID0 Register, see ARM GenericInterrupt Controller Architecture Specification0xFF4 GICD_CIDR1 RO 0xF0 Component ID1 Register, see ARM GenericInterrupt Controller Architecture Specification0xFF8 GICD_CIDR2 RO 0x05 Component ID2 Register, see ARM GenericInterrupt Controller Architecture Specification0xFFC GICD_CIDR3 RO 0xB1 Component ID3 Register, see ARM GenericInterrupt Controller Architecture Specificationa. You cannot modify the secure copy of this register if CFGSDISABLE is asserted.b. This register is only accessible with a Secure access.c. The reset value for the register that contains the SGI and PPI interrupts is 0x0000FFFF because SGIs are always enabled.d. Changing the value of a priority field in the GICD_IPRIORITYRn register changes the priority of an active interrupt.e. SPIs are not statically configured in hardware.f. For Cortex-A15 configuration with only one processor, these registers are RAZ/WI.g. The reset value for the register that contains the SGI interrupts is 0xAAAAAAAA. The reset value for the register that contains the PPI interruptsis 0x55540000. The reset value for the registers that contain the SPI interrupts is 0x55555555.h. The GICD_SGIR has no effect when the GICD_CTLR bit settings disable the Distributor.8.3.2 Distributor register descriptionsThis section only describes registers whose implementation is specific to the Cortex-A15MPCore processor. All other registers are described in the ARM Generic Interrupt ControllerArchitecture Specification. Table 8-3 on page 8-8 provides cross references to individualregisters.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 8-9ID062913Non-Confidential