ARM Cortex-A15 MPCore Processor Technical Reference Manual

Memory Management Unit5.1 About the MMUThe Cortex-A15 MPCore processor implements the Extended VMSAv7 MMU. The MMUsupports:• ARMv7-A Virtual Memory System Architecture (VMSA).• Security Extensions.• Large Physical Address Extensions (LPAE).• Virtualization Extensions.The Extended VMSAv7 MMU controls address translation, access permissions, and memoryattributes determination and checking, for memory accesses.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition for a fullarchitectural description of the Extended VMSAv7.NoteThe Cortex-A15 MPCore processor does not support the Transient attribute in the LPAE. Useof this attribute results in UNPREDICTABLE behavior.The MMU controls table walk hardware that accesses translation tables in memory. The MMUworks with the L1 and L2 memory system to translate virtual addresses to physical addresses.The MMU enables fine-grained memory system control through a set of virtual-to-physicaladdress mappings and memory attributes held in the L1 and L2 Translation Look-aside Buffers(TLBs).The Cortex-A15 MMU features include the following:• 32-entry fully-associative L1 instruction TLB.• Two separate 32-entry fully associative L1 TLBs for data load and store pipelines.• 4-way set-associative 512-entry L2 TLB in each processor.• Intermediate table walk caches.• The TLB entries contain a global indicator or an Address Space Identifier (ASID) topermit context switches without TLB flushes.• The TLB entries contain a Virtual Machine Identifier (VMID) to permit virtual machineswitches without TLB flushes.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 5-2ID062913Non-Confidential