ARM Cortex-A15 MPCore Processor Technical Reference Manual

Signal DescriptionsA.3 Reset signalsSignal Type DescriptionTable A-2 shows the reset and reset control signals. The value of N is one less than the numberof processors in your design.See Clocking and resets on page 2-8 for more information.Table A-2 Reset signalsnCPUPORESET[N:0] Input Individual processor resets:0 Apply reset to processor that includes NEON and VFP, Debug, PTM, breakpointand watchpoint logic.1 Do not apply reset to processor that includes NEON and VFP, Debug, PTM,breakpoint and watchpoint logic.nCORERESET[N:0] Input Individual processor reset excluding Debug and PTM:0 Apply reset to processor that includes NEON and VFP, but excludes Debug,PTM, breakpoint and watchpoint logic.1 Do not apply reset to processor that includes NEON and VFP, but excludesDebug, PTM, breakpoint and watchpoint logic.nCXRESET[N:0] Input Individual processor NEON and VFP resets:0 Apply reset to NEON and VFP.1 Do not apply reset to NEON and VFP.nDBGRESET[N:0] Input Individual processor Debug and PTM resets:0 Apply reset to Debug, PTM, breakpoint and watchpoint logic.1 Do not apply reset to Debug, PTM, breakpoint and watchpoint logic.nL2RESET Input L2 reset:0 Apply reset to shared L2 memory system controller.1 Do not apply reset to shared L2 memory system controller.L2RSTDISABLE Input L2 cache hardware reset disable:0 L2 cache is reset by hardware.1 L2 cache is not reset by hardware.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. A-4ID062913Non-Confidential