ARM Cortex-A15 MPCore Processor Technical Reference Manual

Programmers Model3.4 Security Extensions architectureThe Security Extensions architecture facilitate the development of secure applications. Thissection describes the following:• System boot sequence.• Security Extensions configuration write access disable.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition for moreinformation.3.4.1 System boot sequenceCautionThe Security Extensions enable the development of a more secure software environment. Thetechnology does not protect the processor from hardware attacks, and you must make sure thatthe hardware containing the boot code is appropriately secure.The processor always boots in the privileged Supervisor mode in the Secure state, with SCR.NSset to 0. See Secure Configuration Register on page 4-63. This means that code that does notattempt to use the Security Extensions always runs in the Secure state. If the software uses bothSecure and Non-secure states, the less trusted software, such as a complex operating system andapplication code running under that operating system, executes in Non-secure state, and themost trusted software executes in the Secure state.The following sequence is expected to be typical use of the Security Extensions:1. Exit from reset in Secure state.2. Configure the security state of memory and peripherals. Some memory and peripheralsare accessible only to the software running in Secure state.3. Initialize the secure operating system. The required operations depend on the operatingsystem, and include initialization of caches, MMU, exception vectors, and stacks.4. Initialize Secure Monitor software to handle exceptions that switch execution between theSecure and Non-secure operating systems.5. Optionally lock aspects of the secure state environment to additional configuration.6. Pass control through the Secure Monitor software to the Non-secure OS with an SMCinstruction.7. Enable the Non-secure operating system to initialize. The required operations depend onthe operating system, and typically include initialization of caches, MMU, exceptionvectors, and stacks.The overall security of the software depends on the system design, and on the secure softwareitself.3.4.2 Security Extensions configuration write access disableThe processor pin CP15SDISABLE disables write access to certain registers in the CP15System Control Coprocessor. There is one CP15SDISABLE input for each processor. Attemptsto write to these registers when CP15SDISABLE is HIGH result in an Undefined Instructionexception. Reads from the registers are still permitted.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 3-5ID062913Non-Confidential