ARM Cortex-A15 MPCore Processor Technical Reference Manual

RevisionsTable B-8 Differences between issue G and issue H (continued)Change Location AffectsAdded clarification to the description of the PoU and PoCfootnotesTable 4-20 on page 4-17All revisionsUpdated bits[23:20] of the Main ID Register Main ID Register on page 4-27 r3p3Updated description for the Auxiliary Control Register Auxiliary Control Register on page 4-57 All revisionsUpdated description for the Coprocessor Access ControlRegisterClarified description for the Non-Secure Access ControlRegisterUpdated description for bit[11] TDRA of the Hyp DebugConfiguration RegisterUpdated description for bit[9] TDA of the Hyp DebugConfiguration RegisterAdded a note in the MMU chapter to state that theCortex-A15 MPCore processor does not support theTransient attribute in the Large Physical Address Extensions(LPAE)The processor no longer supports the use of the Prefetch bitin the L2 cache replacement algorithm. Bit[9] of theL2ACTLR is removed.Added a note to the L2 Prefetch Control Register descriptionto indicate that setting a value of 0x400 to this register disablesall the hardware prefetchCoprocessor Access Control Register on page 4-62Non-Secure Access Control Register on page 4-65Hyp Debug Configuration Register on page 4-69Hyp Debug Configuration Register on page 4-69About the MMU on page 5-2L2 Auxiliary Control Register on page 4-100L2 Prefetch Control Register on page 4-103All revisionsAll revisionsAll revisionsAll revisionsAll revisionsr2p2, r3p0,r3p1, andr3p2All revisionsUpdate description for the Write-Through memory type Write-Through on page 6-8 All revisionsUpdate description for the Non-Cacheable memory type Non-Cacheable on page 6-8 All revisionsAdded a note to indicate that any valid requests issued to theCortex-A15 MPCore processor on the AC channel whenBROADCASTINNER and BROADCASTOUTER areboth deasserted, cause UNPREDICTABLE resultUpdated description for the GICD_IPRIORITYRn register toindicate that changing the value of a priority field in theGICD_IPRIORITYRn register changes the priority of anactive interrupt.Added a footnote to the description of theGICD_ITARGETSR registers to state that no SPIs arestatically configured in hardware.Added a footnote to the description of the GICD_SGIRregister to indicate that this register has no effect when theGICD_CTLR bit settings disable the Distributor.Table 7-5 on page 7-16Table 8-3 on page 8-8Table 8-3 on page 8-8Table 8-3 on page 8-8All revisionsAll revisionsAll revisionsAll revisionsClarified definition of the OS Lock Access Register OS Lock Access Register on page 10-22 All revisionsUpdated description for bit[1] Core Warm Reset Request bitof the DBGPRCRDevice Powerdown and Reset Control Register onpage 10-24All revisionsARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. B-6ID062913Non-Confidential