ARM Cortex-A15 MPCore Processor Technical Reference Manual

Functional DescriptionNoteAfter a processor reset, cacheable memory is not accessible until the MMU is enabled.Any architectural state to be restored before the MMU is enabled must therefore be storedin non-cacheable memory.7. Execute an ISB instruction to ensure that all of the CP15 register changes from theprevious steps have been committed.8. Execute a DSB instruction to ensure that all cache, TLB and branch predictor maintenanceoperations issued by any processor in the multiprocessor before the SMP bit was clearedhave completed. In addition, this ensures that all state saving has completed.9. Execute a WFI instruction and wait until the STANDBYWFI output is asserted, to indicatethat the processor is in idle and low power state.10. Repeat the previous steps for all processors, and wait for all STANDBYWFI outputs tobe asserted.11. The SoC asserts the input pin ACINACTM to idle the AXI master interface after allresponses are received and before it sends any new transactions on the interface. The SoCasserts the input pin AINACTS to idle the ACP slave interface after all responses arereceived and before it sends any new transactions on the interface. When the L2 hascompleted the outstanding transactions for the AXI master and slave interfaces,STANDBYWFIL2 is asserted to indicate that L2 memory system is idle.If the SoC asserts ACVALIDM while ACINACTM is asserted, then ACINACTM mustbe deasserted for the request to be accepted. If the SoC asserts ARVALIDS, AWVALIDS,or WVALIDS while AINACTS is asserted, then AINACTS must be deasserted for therequest to be accepted.12. When all processors STANDBYWFI and STANDBYWFIL2 are asserted, theCortex-A15 MPCore processor is ready to enter Dormant mode.13. Activate the L2 cache RAM input clamps by asserting the nISOLATEL2MISC inputsLOW.14. Remove power from the processors, NEON and VFP unit, Debug, and L2 control powerdomains.To exit Dormant mode, apply the following sequence:1. Apply a normal powerup reset sequence. You must apply resets to the processors, NEONand VFP unit, Debug, and the L2 memory system logic until power is restored. Duringthis reset sequence, L2RSTDISABLE must be held HIGH to disable the L2 cachehardware reset mechanism.2. When power has been restored, release the L2 cache RAM input clamps.3. Continue a normal powerup reset sequence with L2RSTDISABLE held HIGH. TheL2RSTDISABLE must be held HIGH for a minimum of 32 CLK cycles after thedeasserting edge of nL2RESET.4. The architectural state must be restored, if required.Processor powerdown modeThe Cortex-A15 MPCore processor supports processor powerdown mode where all theCortex-A15 MPCore processor power domains are shut down and all state is lost.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 2-36ID062913Non-Confidential