ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-45 ID_ISAR4 bit assignments (continued)Bits Name Function[11:8] Writeback_instrs Indicates support for writeback addressing modes:0x1Processor supports all writeback addressing modes defined in ARMv7architecture.[7:4] WithShifts_instrs Indicates support for instructions with shifts.0x4Processor supports:• LDRBT, LDRT, STRBT, and STRT instructions.• LDRHT, LDRSBT, LDRSHT, and STRHT instructions.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition for moreinformation.[3:0] Unpriv_instrs Indicates the supported unprivileged instructions.0x2Processor supports:• Shifts of loads and stores over the range LSL 0-3.• Constant shift options, both on load/store and other instructions.• Register-controlled shift options.To access the ID_ISAR4, read the CP15 register with:MRC p15, 0, , c0, c2, 4 ; Read Instruction Set Attribute Register 44.3.20 Instruction Set Attribute Register 5ID_ISAR5 is reserved, so this register is always RAZ/WI.4.3.21 Cache Size ID RegisterThe CCSIDR characteristics are:PurposeProvides information about the architecture of the caches.Usage constraints The CCSIDR is:• A read-only register.• Common to the Secure and Non-secure states.• Only accessible from PL1 or higher.ConfigurationsThere is one CCSIDR for each cache that it can access. The CSSELRselects which Cache Size ID Register is accessible.Attributes See the register summary in Table 4-2 on page 4-4.Figure 4-18 on page 4-49 shows the CCSIDR bit assignments.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-48ID062913Non-Confidential