ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-1 describes the column headings that the CP15 register summary tables use throughoutthis chapter.Table 4-1 Column headings definition for CP15 register summary tablesColumn nameCRnOp1CRmOp2NameResetDescriptionDescriptionRegister number within the system control coprocessorOpcode_1 value for the registerOperational register number within CRnOpcode_2 value for the registerShort form architectural, operation, or code name for the registerReset value of registerCross-reference to register description4.2.1 c0 registersTable 4-2 shows the 32-bit wide CP15 system control registers when CRn is c0.Op1 CRm Op2 Name Reset Description0 c0 0 MIDR 0x414FC0F0 Main ID Register on page 4-271 CTR 0x8444C004 a Cache Type Register on page 4-282 TCMTR 0x00000000 TCM Type Register on page 4-293 TLBTR 0x00000000 TLB Type Register on page 4-29Table 4-2 c0 register summary4, 7 MIDR 0x414FC0F0 Aliases of Main ID Register, Main ID Register onpage 4-275 MPIDR - b Multiprocessor Affinity Register on page 4-296 REVIDR 0x00000000 Revision ID Register on page 4-30c1 0 ID_PFR0 0x00001131 Processor Feature Register 0 on page 4-311 ID_PFR1 0x00011011 Processor Feature Register 1 on page 4-322 ID_DFR0 0x02010555 Debug Feature Register 0 on page 4-333 ID_AFR0 0x00000000 Auxiliary Feature Register 0 on page 4-344 ID_MMFR0 0x10201105 Memory Model Feature Register 0 on page 4-345 ID_MMFR1 0x20000000 Memory Model Feature Register 1 on page 4-366 ID_MMFR2 0x01240000 Memory Model Feature Register 2 on page 4-377 ID_MMFR3 0x02102211 Memory Model Feature Register 3 on page 4-38c2 0 ID_ISAR0 0x02101110 Instruction Set Attribute Register 0 on page 4-401 ID_ISAR1 0x13112111 Instruction Set Attribute Register 1 on page 4-412 ID_ISAR2 0x21232041 Instruction Set Attribute Register 2 on page 4-43ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-4ID062913Non-Confidential