ARM Cortex-A15 MPCore Processor Technical Reference Manual

NEON and VFP UnitTable 14-7 shows the MVFR0 bit assignments.Table 14-7 MVFR0 bit assignmentsBits Name Function[31:28] VFP rounding modes Indicates the rounding modes supported by the VFP floating-point hardware:0x1Supported.[27:24] Short vectors Indicates the hardware support for VFP short vectors:0x0Not supported.[23:20] Square root Indicates the hardware support for VFP square root operations:0x1Supported.[19:16] Divide Indicates the hardware support for VFP divide operations:0x1Supported.[15:12] VFP exception trapping Indicates whether the VFP hardware implementation supports exception trapping:0x0Not supported.[11:8] Double precision Indicates the hardware support for VFP double-precision operations:0x2VFPv4 double-precision supported.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition formore information.[7:4] Single precision Indicates the hardware support for VFP single-precision operations:0x2VFPv4 single-precision supported.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition formore information.[3:0] A_SIMD registers Indicates support for the Advanced SIMD register bank:0x232 x 64-bit registers supported.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition formore information.Floating-Point Exception RegisterThe FPEXC characteristics are:PurposeProvides a global enable for the Advanced SIMD and VFP extensions, andindicates how the state of these extensions is recorded.Usage constraints Only accessible from PL1 or higher.ConfigurationsAvailable if VFP is implemented. The FPEXC register is a Configurableaccess register which is a system control register that secure software canconfigure the access to. When the settings in the CPACR, see CoprocessorAccess Control Register on page 4-62, permit access to the FPEXCregister:• It is accessible in Non-secure state only if the NSACR.{CP11,CP10} bits are both set to 1. See Non-Secure Access ControlRegister on page 4-65.• Bits in the HCPTR, see Hyp Coprocessor Trap Register onpage 4-71, also control Non-secure access to the register.Attributes See the register summary in Table 14-3 on page 14-6.Figure 14-5 on page 14-13 shows the FPEXC bit assignments.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 14-12ID062913Non-Confidential