ARM Cortex-A15 MPCore Processor Technical Reference Manual

Programmers Model3.2 Execution environment supportFor the Cortex-A15 MPCore processor, ARM deprecates any use of the ThumbEE instructionset and provides a trivial implementation of the Jazelle Extension.This means that:• Jazelle state is not supported, that is, the processor does not accelerate the execution ofany Java bytecodes.• The BXJ instruction behaves as a BX instruction.• The processor supports ThumbEE state only to support legacy code that uses ThumbEEinstructions.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition.Table 3-1 shows the Jazelle register instruction summary and the response to the instructions.Register Instruction ResponseJazelle ID (JIDR) a MRC p14, 7, , c0, c0, 0 Reads as zero bTable 3-1 Jazelle register instruction summaryMCR p14, 7, , c0, c0,0A write causes an undefined exception regardless ofprocessor modeJazelle Main Configuration (JMCR) c MRC p14, 7, , c2, c0, 0 Reads as zero dMCR p14, 7, , c2, c0, 0Ignore writesJazelle OS Control (JOSCR) e MRC p14, 7, , c1, c0, 0 Reads as zeroMCR p14, 7, , c1, c0, 0Ignore writesa. Accessible from all privilege levels.b. Can cause a trap to Hyp mode depending on the TIDO bit set in the HCR.c. Write-only accessible in unprivileged level, read-write accessible at PL1 or higher.d. Can cause a trap to Hyp mode depending on the TJDBX bit set in the HSTR.e. Accessible from PL1 or higher.NoteBecause no hardware acceleration is present in the processor when the BXJ instruction is used,the BX instruction is invoked.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 3-3ID062913Non-Confidential