ARM Cortex-A15 MPCore Processor Technical Reference Manual

Generic Interrupt ControllerTable 8-5 shows the GICD_IIDR bit assignments.Table 8-5 GICD_IIDR bit assignmentsBits Name Description[31:24] ProductID Indicates the product ID of the GIC:0x00 Product ID.[23:20] - Reserved, RAZ[19:16] Variant Indicates the major revision number of the GIC:0x0Variant number.[15:12] Revision Indicates the minor revision number of the GIC:0x0Revision number.[11:0] Implementer Indicates the implementer:0x43B ARM implementation.Interrupt Configuration RegisterThe GICD_ICFGR provides a 2-bit field that describes the configuration for each interrupt thatthe GIC supports.The options for each bit-pair depend on the interrupt type as follows:SGIPPIThe bits are read-only and a bit-pair always reads as b10 because SGIs areedge-triggered.The bits are read-only and a bit-pair always reads as b01. Table 8-6 shows that thePPIs are implemented as level-sensitive.Table 8-6 PPI implementationInterrupt Name Level-sensitivePPI6 Virtual Maintenance interrupt active-HIGHPPI5 Hypervisor timer event active-LOWPPI4 Virtual timer event active-LOWPPI3 Legacy nIRQ pin active-LOWPPI2 Non-secure physical timer event active-LOWPPI1 Secure physical timer event active-LOWPPI0 Legacy nFIQ pin active-LOWSPIThe Least Significant Bit (LSB) of the bit-pair is read-only and is always 1. Youcan program the Most Significant Bit (MSB) of the bit-pair to alter the triggeringsensitivity as follows:b01b11Interrupt is active-HIGH level-sensitive.Interrupt is rising edge-sensitive.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 8-12ID062913Non-Confidential