ARM Cortex-A15 MPCore Processor Technical Reference Manual

Performance Monitor UnitTable 11-7 PMU events (continued)EventnumberEvent mnemonicPMU event bus(to external) aPMU eventbus (to trace) aEvent name0x1D BUS_CYCLES - [32] Bus cycle0x40 L1D_CACHE_LD [15] [33] Level 1 data cache access, read0x41 L1D_CACHE_ST [16] [34] Level 1 data cache access, write0x42 L1D_CACHE_REFILL_LD - [35] Level 1 data cache refill, read0x43 L1D_CACHE_REFILL_ST - [36] Level 1 data cache refill, write0x46 L1D_CACHE_WB_VICTIM - [37] Level 1 data cache write-back, victim0x47 L1D_CACHE_WB_CLEAN - [38] Level 1 data cache write-back, cleaningand coherency0x48 L1D_CACHE_INVAL - [39] Level 1 data cache invalidate0x4C L1D_TLB_REFILL_LD [17] [40] Level 1 data TLB refill, read0x4D L1D_TLB_REFILL_ST [18] [41] Level 1 data TLB refill, write0x50 L2D_CACHE_LD [19] [42] Level 2 data cache access, read0x51 L2D_CACHE_ST [20] [43] Level 2 data cache access, write0x52 L2D_CACHE_REFILL_LD - [44] Level 2 data cache refill, read0x53 L2D_CACHE_REFILL_ST - [45] Level 2 data cache refill, write0x56 L2D_CACHE_WB_VICTIM - [46] Level 2 data cache write-back, victim0x57 L2D_CACHE_WB_CLEAN - [47] Level 2 data cache write-back, cleaningand coherency0x58 L2D_CACHE_INVAL - [48] Level 2 data cache invalidate0x60 BUS_ACCESS_LD - [49] Bus access, read0x61 BUS_ACCESS_ST - [50] Bus access, write0x62 BUS_ACCESS_SHARED - [52:51] Bus access, Normal, Cacheable,Shareable0x63 BUS_ACCESS_NOT_SHARED - [54:53] Bus access, not Normal, Cacheable,Shareable0x64 BUS_ACCESS_NORMAL - [56:55] Bus access, normal0x65 BUS_ACCESS_PERIPH - [58:57] Bus access, peripheral0x66 MEM_ACCESS_LD - [59] Data memory access, read0x67 MEM_ACCESS_ST - [60] Data memory access, write0x68 UNALIGNED_LD_SPEC - [61] Unaligned access, read0x69 UNALIGNED_ST_SPEC - [62] Unaligned access, write0x6A UNALIGNED_LDST_SPEC - [64:63] Unaligned access0x6C LDREX_SPEC [21] [65] Exclusive instruction speculativelyexecuted, LDREXARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 11-16ID062913Non-Confidential