ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlThe data returned from accessing L1-I indirect predictor RAM are:IL1DATA2 32'b0.IL1DATA1 32'b0.IL1DATA0 Indirect predictor data[31:0].Figure 4-49 shows the RAMINDEX bit assignments for accessing L1-D tag RAM.31 24 23 19 18 17 14 136 50RAMID = 0x08ReservedReservedPhysical address [13:6]ReservedWayFigure 4-49 RAMINDEX bit assignments for L1-D tag RAMThe RAMINDEX address bits for accessing L1-D tag RAM are:WayPA[13:8]PA[7:6]Way select.Row select.Bank select.The data returned from accessing L1-D tag RAM are:DL1DATA3 32'b0.DL1DATA2 32'b0.DL1DATA1 Tag ECC[6:0].DL1DATA0 Tag data[28:0].Figure 4-50 shows the RAMINDEX bit assignments for accessing L1-D data RAM.31 24 23 19 18 17 14 13 3 2 0RAMID = 0x09ReservedUnusedPhysical address [13:3]WayReservedFigure 4-50 RAMINDEX bit assignments for L1-D data RAMThe RAMINDEX address bits for accessing L1-D data RAM are:WayPA[13:6]PA[5:4]PA[3]Way select.Set select.Bank select.Upper or lower doubleword within the quadword.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-95ID062913Non-Confidential