ARM Cortex-A15 MPCore Processor Technical Reference Manual

Programmers Model3.8 Modes of operation and executionThis section describes the instruction set states and modes of the Cortex-A15 MPCore processorin:• Operating states.3.8.1 Operating statesThe processor has the following instruction set states controlled by the T bit and J bit in theCPSR.ARM stateThumb stateThumbEE stateThe processor executes 32-bit, word-aligned ARM instructions.The processor executes 16-bit and 32-bit, halfword-aligned Thumbinstructions.The processor executes a variant of the Thumb instruction set designed asa target for dynamically generated code. This is code compiled on thedevice either shortly before or during execution from a portable bytecodeor other intermediate or native representation.The J bit and the T bit determine the instruction set used by the processor. Table 3-2 shows theencoding of these bits.Table 3-2 CPSR J and T bit encodingJ T Instruction set state0 0 ARM0 1 Thumb1 1 ThumbEENote• The processor does not support Jazelle state. This means there is no processor state wherethe J bit is 1 and T bit is 0.• Transition between ARM and Thumb states does not affect the processor mode or theregister contents. See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-Redition for information on entering and exiting ThumbEE state.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 3-10ID062913Non-Confidential