ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 1 Memory Systemcache in Exclusive or Shared state and the PLDW instruction brings the line into the cache inExclusive state. The preload instruction cache, PLDI, is treated as a NOP. PLD and PLDWinstructions are performance hints instructions only and might be dropped in some cases.6.4.8 Error Correction CodeThe L1 data cache supports optional single bit correct and double bit detect error correctionlogic in both the tag and data arrays. The ECC granularity for the tag array is the tag for a singlecache line and the ECC granularity for the data array is a 32-bit word.Because of the ECC granularity in the data array, a write to the array cannot update a portion ofa 4-byte aligned memory location because there is not enough information to calculate the newECC value. This is the case for any store instruction that does not write one or more aligned4-byte regions of memory. In this case, the L1 data memory system reads the existing data inthe cache, merges in the modified bytes, and calculates the ECC from the merged value. The L1memory system attempts to merge multiple stores together to meet the aligned 4-byte ECCgranularity and to avoid the read-modify-write requirement.Single bit ECC errors in the tag or cache are corrected in the background. Because the line isremoved from the L1 cache as part of the correction process, no software intervention isrequired. No exception or interrupt is generated. The CPU Memory Error Syndrome Register,see CPU Memory Error Syndrome Register on page 4-107, is updated to indicate a non-fatalerror.Double bit ECC errors in the tag or cache are detected and an imprecise Data Abort is triggered.The line that contains the error is evicted from the cache. When a double bit error is reported,you must assume that data corruption has occurred and handle this appropriately.For any detected ECC error in the L1 memory system, the CPU Memory Error SyndromeRegister is updated. For the first error reported, the register is updated with information for theRAM, bank, way, and index that contain the error. If that same location reports multiple errors,the repeat error count is incremented. If any other RAM locations report errors, the other errorcount is incremented. Double-bit ECC errors set the fatal bit. When the register is written withzeros, the register clears all counts and starts to monitor for a new first error again.If a double-bit ECC error triggers an abort in the L1 data memory system, the Auxiliary DataFault Status Register is updated with information for the RAM, bank, set, way, and index thattriggered the abort. See Auxiliary Data Fault Status Register on page 4-81.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 6-11ID062913Non-Confidential