ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control4.3.51 Memory Attribute Indirection Register 1The processor behavior for all implementation-defined encodings in the MAIR1 register isUNPREDICTABLE.4.3.52 Auxiliary Memory Attribute Indirection Register 0The processor behavior for all implementation-defined encodings in the AMAIR0 register isUNPREDICTABLE.4.3.53 Auxiliary Memory Attribute Indirection Register 1The processor behavior for all implementation-defined encodings in the AMAIR1 register isUNPREDICTABLE.4.3.54 Hyp Auxiliary Memory Attribute Indirection Register 0The processor behavior for all implementation-defined encodings in the HAMAIR0 register isUNPREDICTABLE.4.3.55 Hyp Auxiliary Memory Attribute Indirection Register 1The processor behavior for all implementation-defined encodings in the HAMAIR1 register isUNPREDICTABLE.4.3.56 FCSE Process ID RegisterThe processor does not implement Fast Context Switch Extension (FCSE), so this register isalways RAZ/WI.4.3.57 Instruction L1 Data n RegisterThe IL1Datan, where n is from 0 to 2, characteristics are:PurposeHolds the instruction side L1 array information returned by theRAMINDEX write operation. See RAM Index Register on page 4-91 formore information.NoteBecause the data, BTB, GHB, and TLB arrays are greater than 32-bitswide, the processor contains multiple IL1Data registers, to hold the arrayinformation.Usage constraints The IL1Datan is:• A read/write register.• Common to the Secure and Non-secure states.• Only accessible from PL1 or higher.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-14 on page 4-13.Figure 4-40 on page 4-90 shows the IL1Datan bit assignments.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-89ID062913Non-Confidential