ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 2 Memory System• Each tag slice adds 2 cycles and affects the L2 tag, snoop tag, dirty, and prefetch stridequeue RAMs.• Setting tag setup to 1 adds 1 cycle.• Slice and setup have priority over programmed latency in determining the total adjustedRAM latency.Example 7-1 shows a tag RAM access with 3 cycles total RAM latency.Example 7-1 Tag RAM access with 3 cycles total latencyWhen tag slice = 0, L2CTLR[9] = 0, L2CTLR[8:6] = 3'b010, the following applies:• No slice cycle.• No setup cycle.• 3 cycles tag RAM access.• 3 cycles total tag RAM latency.Example 7-2 shows a tag RAM access with 5 cycles total RAM latency.Example 7-2 Tag RAM access with 5 cycles total latencyWhen tag slice = 1, L2CTLR[9] = 1, L2CTLR[8:6] = 3'b010, the following applies:• 2 slice cycles.• 1 setup cycle.• 2 cycles tag RAM access adjusted because of slice and setup values.• 5 cycles total tag RAM latency.Table 7-2 shows the adjusted L2 data RAM latency with the register slice and setup factored in.Table 7-2 L2 data RAM latency with slice and setup factored inTotal adjusted data RAM latencyL2CTLR[2:0]Data slice = 0Data setup = 0Data slice = 0Data setup = 1Data slice = 1Data setup = 0Data slice = 1Data setup = 1Data slice = 2Data setup = 0Data slice = 2Data setup = 1000 a 2 3 4 5 6 7001 2 3 4 5 6 7010 3 4 5 6 7 8011 4 5 6 7 8 8100 5 6 7 8 8 8101 6 7 8 8 8 8110 7 8 8 8 8 8111 8 8 8 8 8 8a. This is the reset value.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 7-6ID062913Non-Confidential