R&S FSQ Signal Analyzer - Rohde & Schwarz

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R&S FSQ Instrument Functions 4.12.2 Online Interface Digital Baseband Interface - Option R&S FSQ-B17 The online interface is an LVDS interface, compatible with LVDS channel link introduced by National Semiconductor. Compatible receiver and deserializer: DS90CR486 (also suitable: DS90CR484) For additional information please refer to: http://www.national.com/appinfo/lvds/files/channellink_design_guide.pdf http://www.national.com/ds/DS/DS90CR486.pdf Fig. 4.19 shows a general overview of the IQ data interface. Fig. 4.19 R&S FSQ LVDS interface connection overview Fig. 4.20 shows the functional timing diagram of the interface. Fig. 4.20 Functional timing diagram 4.274 Operating Manual 1313.9681.12 - 01
R&S FSQ Instrument Functions 4.12.3 Signal Description 4.12.4 Signal Assignment 4.12.4.1 Connector Fig. 4.21 Connector on R&S FSQ rear panel, connector front view. Digital Baseband Interface - Option R&S FSQ-B17 Clock: Sample clock from the R&S FSQ with a frequency of 81.6 MHz. It writes the parallel IQ data into the channel link transmitter with the positive edge. The user application must read the transmitted data out of the channel link receiver also with the positive edge of this signal. I_DATA0:19: Real data 20 bits Q_DATA0:19: Imaginary data 20 bits ENABLE: Signals the validity of individual data during a data transmission. DATA_VALID: Defines the start and stop event of the data transmission. The transmission starts on the rising edge of DATA_VALID and stops on the falling edge. Data are only valid while DATA_VALID is "high". The user-defined sampling rate can be lower than the fixed 81.6 MHz data rate of the interface. When the sampling rate is lower than 81.6 MHz, not all transmitted data are valid samples. The ENABLE bit in state "high" indicates the valid samples. Connector type: 26 pin female 0.050" Mini D Ribbon connector (e.g.: 3M 102XX- 1210VE series) 4.12.4.2 Pin description: This table shows the multiplexed data at the output of the LVDS transmitter. DS90CR483 is used as transmitter. For further information on multiplexing/demultiplexing scheme, please refer to: http://www.national.com/ds.cgi/DS/DS90CR483.pdf) Pin Signal Level 1 reserved for future use 2 GND 0V Ground, shield of pair 1-14, for future use 3 SDAT0_P LVDS Serial data channel 0 positive pin; carries the bits VALID, ENABLE, MARKER_1, Reserve_1, RE_0, RE_1 4 SDAT1_P LVDS Serial data channel 1 positive pin; carries the bits RE_2, RE_3, RE_4, RE_5, RE_6, RE_7 Operating Manual 1313.9681.12 - 01 4.275
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