U. Glaeser

FIGURE 36.1
were introduced; however, not many works have been published on how those architectures were
designed. The latest FPGA devices are provided by companies such as Xilinx, Altera, Actel, and
Lucent. Industrial designers are increasingly capturing their designs using hardware description languages
such as VHDL and Verilog. There are tools developed for FPGAs, which synthesize designs in
VHDL format or other description format. Current synthesis tools for FPGAs are provided by companies
Synopsys, Synplicity, and Leonado Spectrum. Physical design tools perform placement and routing
for FPGAs. Xilinx and Altera provide place/route tools for their own FPGA devices.
Today’s high-volume applications require a fabric with higher complexity and better performance
than FPGAs. Also, shorter development cost and more flexible reconfiguration are required. Several
contributions have been made in FPGA devices toward this direction. Capacity of FPGAs has been
increased. High-density FPGAs are available in the market offering competitive solutions to ASICs and
programmable systems such as DSPs. Hierarchical features have been added into logic and routing
architecture of FPGAs. The new generation of FPGAs have a trend towards embedding coarser grain
units. Most applications require a large amount of storage. Architectural support for implementation of
memory is crucial. Some FPGA devices have embedded memory (RAM, ROM). In addition, implementing
general logic in these embedded arrays of memory blocks is viable. In order to support high repetitive
and data intensive computation on FPGAs more efficiently, arithmetic resources have been developed.
Examples of such enhancement are cascade chain, multipliers, and dedicated adders, etc. Fine-grain
FPGA architectures are shifting towards new architectures where memory blocks, hard IPs, and even
CPUs are being integrated into FPGAs. In these designs the traditional FPGA is not a co-processor, instead
a reconfigurable fabric is embracing all the mentioned components and enabling a much tighter integration
among them. Today, FPGA CAD tools provide integration of macro blocks into designs. Macro
blocks are optimized for area, delay, or power consumption. In addition, placement of such macro blocks
can be predefined in CAD tools such as CoreGEN @ integrated with Xilinx design implementation
tool. MemGen @ and LogiBlox @ in Xilinx tool enable the implementation of embedded memory blocks.
Hence, tool vendors are moving to higher-level optimization. There is better integration between synthesis
and physical design tool.
Flexibility in reconfigurable systems comes at the expense of the reconfiguration time. The amount
of time required to set the function to be implemented on the reconfigurable logic is the configuration
time, which can become a serious bottleneck especially in systems where run-time reconfiguration is
performed [3,4].
© 2002 by CRC Press LLC