U. Glaeser

FIGURE 2.6 A 2-input CMOS NAND gate and the switch-level equivalent circuits for all the possible input
combinations.
FIGURE 2.7 A 2-input CMOS NOR gate.
A 2-input CMOS NAND gate and the switch level equivalent circuits for all the possible input combinations
are shown in Fig. 2.6. This circuit realizes the function F = ( AB)
′ . The generation of the CMOS circuit has
the following steps. For the pull-down network, take the non-inverted expression AB (called the n-expression)
and realize using NMOS transistors. For the pull-up network, find the dual of the n-expression (called the
p-expression) and realize using PMOS transistors. In this example the dual is A + B (p-expression). For the
CMOS NAND gate shown in Fig. 2.6, if any of the inputs is a 0, one of the NMOS transistors will be OFF
and the pull-down network will be open. At the same time one of the PMOS transistors will be ON and the
pull-up network will be closed, and the output will be pulled up to VDD
(logic 1). If all the inputs are high
(logic 1), the pull-down network will be closed and the pull-up network will be open and the output will be
pulled down to ground (logic 0), which is the desired functionality of a NAND gate.
Figure 2.7 illustrates the CMOS realization of a 2-input NOR gate. In Fig. 2.7, the output value is
equal to 0 when either A or B is equal to 1 because one of the NMOS transistors will be ON. But if both
inputs are equal to 0, the series pair of PMOS transistors between VDD
and the output Y will be ON,
resulting in a 1 at the output, which is the desired functionality of a NOR gate. Figure 2.8 illustrates a
2-input CMOS OR gate realized in two different fashions. In the first method, an inverter is connected
to the output of a NOR circuit to obtain an OR circuit. In the second method, we make use of DeMorgan’s
theorem, ( A′
B′
) ′ = A + B,
to realize the OR logic function. It should be noted that the inputs are inverted
in the second method. To realize the CMOS AND gate, the same principles can be used.
CMOS compound gates can be realized using a combination of series and parallel switch structures.
Figure 2.9 shows the CMOS realization of the logic function Y = ( ABC + D)′. The pull-down network is
realized using the n-expression: ABC + D (the noninverted expression of Y). The pull-up network is
realized using the dual of the n-expression, which is equal to (A + B + C)D. In order to further illustrate
© 2002 by CRC Press LLC