U. Glaeser

digitally by first feeding the input to an analog-to-digital converter (ADC) and digitally post-processing the
ADC’s output. An ADC is commonly used in disk-drive read channels since it also allows one to
implement more complex nonlinear receive filters. Although this approach works well at frequencies
lower than 1 GHz, it is very challenging with gigahertz signals because of the required GSamples/sec
converters. Recent research demonstrated a multi-GSamples/sec 4-bit ADC [10] (1 W of power), which
indicates the potential of high data rate conversion albeit with high power dissipation. Instead of a digital
implementation, for less area and power overhead at these high bit rates, a simple 1-tap FIR filter (1 − αD)
has been implemented as a switched-current filter [13] or a switched capacitor filter [47].
31.4 Timing Generation and Recovery
The task of timing recovery essentially determines the timing relationship between the transmitter and
the receiver so that the data can be received with minimal error. Typically, the burden of adjusting the
timing relationship falls on the receiver. Transmitter clocking is much easier where one primarily needs
a low-jitter clock source. 16 The receiver has a more difficult task of recovering the timing from the received
signals.
The prior receiver discussion does not address how to generate the clock for the amplifiers and
samplers. Recovering a clock signal with low timing noise (jitter) and with accurate phase position is the
most difficult challenge for high data rates. The same eye diagram in Fig. 31.13 illustrates the timing
margin of a receiver. To maximize the timing margin, the receiver should sample the data in the middle
of the data-eye. 17 If clocked amplifiers are used, the clock should be in-phase with the data to maximize
the settling time of the amplifier. Furthermore, designs should minimize the jitter of both the sampling
clock and the clock used at the transmitter. Almost all clock recovery circuits use a feedback loop known
as a phase-locked loop (PLL) to adjust the clock phase position and minimize jitter. This section discusses
different PLL architectures and methods to reduce offsets from the ideal sampling position (static phase
offsets) and jitter.
Architectures
A PLL is often used to synchronize the transmitter clock’s phase and frequency 18 to that of a system clock.
In order to transmit phase information along with the data, two methods are commonly used. For short
distances of a wide data bus, source synchronous clocking is a method that transmits a clock in-phase
with the data. Otherwise, prior to transmission, data is encoded to contain periodic data transitions that
can be used to align the receive clock [13,15]. In some systems, the receiver and the transmitter use clocks
with slightly different frequencies. Then the timing recovery PLL has the additional task of recovering
the frequency from the data transitions.
Figure 31.17 shows the architecture of a PLL. Two basic approaches are used: oscillator-based PLLs, and
delay-line-based PLLs or delay-locked loops (DLLs). Both systems are similar feedback loops where a control
voltage (V ctl) adjust the phase of the periodic output signal (clk int) to have a fixed phase relationship with
the input signal (inp ref). To distribute the clock to many receivers, a buffer chain drives the clock line, clk samp.
DLLs control the output phase by directly adjusting the delay of a voltage-controlled delay line (VCDL)
[25]. The control loop integrates the control voltage to drive the phase error to zero. This feedback loop
is a first-order loop and is guaranteed stability, but it is constrained in that the frequency of the input
clock (clk ext or inp ref) determines the frequency of the output signal. Furthermore, the delay elements
limit the maximum and minimum delay of the line. Designing the range to be large enough for all PVT
and starting the loop at the correct delay often require auxiliary circuits. Using an oscillator-based PLL
16
If data is multiplexed, clock phases must be properly positioned. For 2:1 multiplexing, the duty cycle needs to
be 50%.
17
The eye may not be symmetric. Off-center sampling may increase the amplitude of the sampled signal.
18
PLLs are often used to generate a multiplied frequency.
© 2002 by CRC Press LLC