U. Glaeser

Programmable Active Memories (PAM)
A dozen copies of the variant named DECPeRLe-1 found their way into research centers around the
world and were applied to a diverse set of problems [10]. The computing surface was a 4 × 4 array of
XC3090 devices with seven additional FPGAs acting as memory and interface controllers. FPGAs in the
array were connected directly to each of their four neighbours. Devices in each row and column shared
common 16-bit buses, so that there were four 64-bit buses running the length of the array—one for each
geographic direction N, S, E, and W. Static RAM was added to provide the storage lacking in the early
devices used and FIFOs provided elasticity in a high-speed interface to a host processor. Vuillemin et al.
discuss an extensive list of problems to which PAMs were applied [10]: long integer arithmetic, RSA
cryptography, molecular biology, finite differences, neural networks, video compression, image classification,
image analysis, cluster detection, image acquisition, stereo vision, sound synthesis, and Viterbi
decoding.
They consistently applied the following rule in deciding what part of any problem should be allocated
to the hardware:
“Cast the inner loop in PAM hardware; let software handle the rest [10]!”
PAM spawned a successor, PAMETTE, a PCI card with 5 Xilinx 4000 series devices on it [11]. One
device served as the PCI interface with the remaining four arranged in a 2 × 2 matrix. SRAM and DRAM
may be added and provision is made for external connections via a daughter board. A large number of
similar boards—all with the same basic idea: place a number of FPGAs on a card, which may be inserted
into the bus of a suitable host—have been designed by research groups. Several commercial products are
also available.
SPACE
The Scalable Parallel Architecture for Concurrency Experiments (SPACE) machine was developed at the
University of Strathclyde [12]; it was followed by the SPACE-II, built at the University of South Australia
[13]. Both variants used fine-grain FPGAs (Algotronix CAL1024s in SPACE and Xilinx XC6216s in
SPACE 2) as the primary target was the simulation of highly concurrent systems such as digital circuits,
traffic systems, particle flow, and electrical stimuli models of the heart. SPACE 2 processor boards contained
8 XC6216 processor FPGAs and an XC4025 providing a PCI interface to an Alpha host. On each board,
the fine-grained processors are connected in a mesh in order to provide a seamless array of gates on the
board. Additional memory (32 Mb of static RAM) was present on each board. A secondary backplane
allowed high-bandwidth connections between SPACE 2 boards.
Achilles
The Achilles architecture aims to provide much more flexible interconnection patterns: Figure 37.5 shows
the 3-D arrangement in which small PCBs containing a single FPGA are arranged in a vertical “stack”
[14,15]. A limited number of fixed bussed interconnections are provided at the base of the stack, committing
only about one-third of the available I/O pins to fixed interconnect. A second side of the stack is
used for programming and diagnostic connections: this enables the stack to be “gang” programmed—
each FPGA is loaded with an identical program—or individually. The remaining two sides have uncommitted
connections: connectors are provided for groups of eight signals and ribbon cables are used to
connect FPGAs as the target application requires. This system offers wide variations in communication
patterns at the expense of manual reconfiguration.
Applications
The list of applications, which have been successfully implemented in reconfigurable hardware systems,
is long; it includes applications from such diverse areas as:
• Image processing
• Cryptography
© 2002 by CRC Press LLC